Leilei Zhang

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Flex board and flexible module
- Patent number 12,040,262
- Issue date Jul 16, 2024
- Apple Inc.
- Dennis R. Pyper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective soldering with photonic soldering technology
- Patent number 12,041,728
- Issue date Jul 16, 2024
- Apple Inc.
- Maryam Rahimi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
System in package for lower z height and reworkable component assembly
- Patent number 11,462,461
- Issue date Oct 4, 2022
- Apple Inc.
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical module and perpendicular pin array interconnect for stacke...
- Patent number 10,602,612
- Issue date Mar 24, 2020
- Apple Inc.
- Lan H. Hoang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Process for manufacturing a printed circuit board having high densi...
- Patent number 10,219,387
- Issue date Feb 26, 2019
- NVIDIA Corporation
- Leilei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit package with a conductive grid formed in a packa...
- Patent number 9,831,189
- Issue date Nov 28, 2017
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stiffening electronic packages by disposing a stiffener ring betwee...
- Patent number 9,760,132
- Issue date Sep 12, 2017
- NVIDIA Corporation
- Leilei Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Open solder mask and or dielectric to increase lid or ring thicknes...
- Patent number 9,716,051
- Issue date Jul 25, 2017
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low-profile chip package with modified heat spreader
- Patent number 9,530,714
- Issue date Dec 27, 2016
- NVIDIA Corporation
- Shantanu Kalchuri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bottom package having routing paths connected to top package and me...
- Patent number 9,502,355
- Issue date Nov 22, 2016
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Offset integrated circuit packaging interconnects
- Patent number 9,478,482
- Issue date Oct 25, 2016
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Variable-size solder bump structures for integrated circuit packaging
- Patent number 9,385,098
- Issue date Jul 5, 2016
- NVIDIA Corporation
- Leilei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method for forming an integrated circuit package
- Patent number 9,368,183
- Issue date Jun 14, 2016
- NVIDIA Corporation
- Leilei Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Substrate build up layer to achieve both finer design rule and bett...
- Patent number 9,368,439
- Issue date Jun 14, 2016
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Absorbing excess under-fill flow with a solder trench
- Patent number 9,368,422
- Issue date Jun 14, 2016
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System, method, and computer program product for affixing a post to...
- Patent number 9,087,830
- Issue date Jul 21, 2015
- NVIDIA Corporation
- Leilei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Microelectronic package with stress-tolerant solder bump pattern
- Patent number 9,082,674
- Issue date Jul 14, 2015
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package having improved coplanarity
- Patent number 9,059,054
- Issue date Jun 16, 2015
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lead-free structures in a semiconductor device
- Patent number 8,410,604
- Issue date Apr 2, 2013
- Xilinx, Inc.
- Laurene Yip
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Barrier layer to prevent conductive anodic filaments
- Patent number 8,143,532
- Issue date Mar 27, 2012
- Xilinx, Inc.
- Leilei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of enabling a circuit board analysis
- Patent number 8,063,656
- Issue date Nov 22, 2011
- Xilinx, Inc.
- Pedro R. Ubaldo
- G01 - MEASURING TESTING
Information Patent Grant
Substrate for an integrated circuit package and a method of forming...
- Patent number 7,994,631
- Issue date Aug 9, 2011
- Xilinx, Inc.
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact pad and method of forming a contact pad for an integrated c...
- Patent number 7,821,132
- Issue date Oct 26, 2010
- Xilinx, Inc.
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package and apparatus and method of producing an...
- Patent number 7,807,501
- Issue date Oct 5, 2010
- Xilinx, Inc.
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal lid with improved adhesion to package substrate
- Patent number 7,790,510
- Issue date Sep 7, 2010
- Xilinx, Inc.
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package and apparatus and method of producing an...
- Patent number 7,652,369
- Issue date Jan 26, 2010
- Xilinx, Inc.
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder ball assembly for a semiconductor device and method of fabri...
- Patent number 7,545,028
- Issue date Jun 9, 2009
- Xilinx, Inc.
- Leilei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit package and method of attaching a lid to a subst...
- Patent number 7,388,284
- Issue date Jun 17, 2008
- Xilinx, Inc.
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal lid with improved adhesion to package substrate
- Patent number 7,342,298
- Issue date Mar 11, 2008
- Xilinx, Inc.
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder ball assembly for a semiconductor device and method of fabri...
- Patent number 7,241,640
- Issue date Jul 10, 2007
- Xilinx, Inc.
- Leilei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
ELECTRONIC CIRCUIT PACKAGES
- Publication number 20240080970
- Publication date Mar 7, 2024
- Apple Inc.
- Leilei ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flex Board and Flexible Module
- Publication number 20230026254
- Publication date Jan 26, 2023
- Apple Inc.
- Dennis R. Pyper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System In Package for Lower Z Height and Reworkable Component Assembly
- Publication number 20210384113
- Publication date Dec 9, 2021
- Apple Inc.
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Selective Soldering with Photonic Soldering Technology
- Publication number 20210185831
- Publication date Jun 17, 2021
- Apple Inc.
- Maryam Rahimi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Selective Soldering with Photonic Soldering Technology
- Publication number 20210043597
- Publication date Feb 11, 2021
- Apple Inc.
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR A HIGH BANDWIDTH B...
- Publication number 20150243610
- Publication date Aug 27, 2015
- NVIDIA Corporation
- Leilei ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE HAVING IMPROVED COPLANARITY
- Publication number 20150216066
- Publication date Jul 30, 2015
- NVIDIA Corporation
- Leilei Zhang
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
INTEGRATED CIRCUIT PACKAGE HAVING IMPROVED COPLANARITY
- Publication number 20150194360
- Publication date Jul 9, 2015
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC PACKAGE WITH STRESS-TOLERANT SOLDER BUMP PATTERN
- Publication number 20150102483
- Publication date Apr 16, 2015
- NVIDIA Corporation
- Leilei ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STIFFENING ELECTRONIC PACKAGES
- Publication number 20150077918
- Publication date Mar 19, 2015
- NVIDIA Corporation
- Leilei Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH A CONDUCTIVE GRID FORMED IN A PACKA...
- Publication number 20150016043
- Publication date Jan 15, 2015
- NVIDIA Corporation
- Leilei ZHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKAGING SUBSTRATE THAT HAS ELECTROPLATED PADS THAT ARE FREE OF PL...
- Publication number 20150016042
- Publication date Jan 15, 2015
- NVIDIA Corporation
- Leilei ZHANG
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVE WETTING PROCESS TO INCREASE SOLDER JOINT STANDOFF
- Publication number 20140362550
- Publication date Dec 11, 2014
- Leilei ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR MANUFACTURING A PRINTED CIRCUIT BOARD HAVING HIGH DENSI...
- Publication number 20140208590
- Publication date Jul 31, 2014
- NVIDIA Corporation
- Leilei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
ABSORBING EXCESS UNDER-FILL FLOW WITH A SOLDER TRENCH
- Publication number 20140175681
- Publication date Jun 26, 2014
- NVIDIA Corporation
- Leilei ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW-PROFILE CHIP PACKAGE WITH MODIFIED HEAT SPREADER
- Publication number 20140167216
- Publication date Jun 19, 2014
- NVIDIA Corporation
- Shantanu KALCHURI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VARIABLE-SIZE SOLDER BUMP STRUCTURES FOR INTEGRATED CIRCUIT PACKAGING
- Publication number 20140138823
- Publication date May 22, 2014
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OFFSET INTEGRATED CIRCUIT PACKAGING INTERCONNECTS
- Publication number 20140138824
- Publication date May 22, 2014
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE BUILD UP LAYER TO ACHIEVE BOTH FINER DESIGN RULE AND BETT...
- Publication number 20140124944
- Publication date May 8, 2014
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPEN SOLDER MASK AND OR DIELECTRIC TO INCREASE LID OR RING THICKNES...
- Publication number 20140124913
- Publication date May 8, 2014
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-SOLDER MASK DEFINED COPPER PAD AND EMBEDDED COPPER PAD TO REDUC...
- Publication number 20140124254
- Publication date May 8, 2014
- NVIDIA Corporation
- Leilei ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED INTEGRATED CIRCUIT PACKAGE LID HEIGHT
- Publication number 20140117527
- Publication date May 1, 2014
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGING SUBSTRATE WITH RELIABLE VIA STRUCTURE
- Publication number 20130313720
- Publication date Nov 28, 2013
- Leilei ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PREPARING A SUBSTR...
- Publication number 20130256873
- Publication date Oct 3, 2013
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CONTROLLING WARPIN...
- Publication number 20130251967
- Publication date Sep 26, 2013
- NVIDIA Corporation
- Leilei Zhang
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR AFFIXING A POST TO...
- Publication number 20130252414
- Publication date Sep 26, 2013
- NVIDIA Corporation
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEAD-FREE STRUCTURES IN A SEMICONDUCTOR DEVICE
- Publication number 20120098130
- Publication date Apr 26, 2012
- Xilinx, Inc.
- Laurene Yip
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BARRIER LAYER TO PREVENT CONDUCTIVE ANODIC FILAMENTS
- Publication number 20100193229
- Publication date Aug 5, 2010
- Xilinx, Inc.
- Leilei Zhang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Contact pad and method of forming a contact pad for an integrated c...
- Publication number 20080303152
- Publication date Dec 11, 2008
- Xilinx, Inc.
- Leilei Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Solder ball assembly for a semiconductor device and method of fabri...
- Publication number 20070246817
- Publication date Oct 25, 2007
- Xilinx, Inc.
- Leilei Zhang
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Leilei Zhang

Person

Patents Grantslast 30 patents

Flex board and flexible module

Selective soldering with photonic soldering technology

System in package for lower z height and reworkable component assembly

Vertical module and perpendicular pin array interconnect for stacke...

Process for manufacturing a printed circuit board having high densi...

Integrated circuit package with a conductive grid formed in a packa...

Stiffening electronic packages by disposing a stiffener ring betwee...

Open solder mask and or dielectric to increase lid or ring thicknes...

Low-profile chip package with modified heat spreader

Bottom package having routing paths connected to top package and me...

Offset integrated circuit packaging interconnects

Variable-size solder bump structures for integrated circuit packaging

Method for forming an integrated circuit package

Substrate build up layer to achieve both finer design rule and bett...

Absorbing excess under-fill flow with a solder trench

System, method, and computer program product for affixing a post to...

Microelectronic package with stress-tolerant solder bump pattern

Integrated circuit package having improved coplanarity

Lead-free structures in a semiconductor device

Barrier layer to prevent conductive anodic filaments

Method of enabling a circuit board analysis

Substrate for an integrated circuit package and a method of forming...

Contact pad and method of forming a contact pad for an integrated c...

Integrated circuit package and apparatus and method of producing an...

Metal lid with improved adhesion to package substrate

Integrated circuit package and apparatus and method of producing an...

Solder ball assembly for a semiconductor device and method of fabri...

Integrated circuit package and method of attaching a lid to a subst...

Metal lid with improved adhesion to package substrate

Solder ball assembly for a semiconductor device and method of fabri...

Patents Applicationslast 30 patents

ELECTRONIC CIRCUIT PACKAGES

Flex Board and Flexible Module

System In Package for Lower Z Height and Reworkable Component Assembly

Selective Soldering with Photonic Soldering Technology

Selective Soldering with Photonic Soldering Technology

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR A HIGH BANDWIDTH B...

INTEGRATED CIRCUIT PACKAGE HAVING IMPROVED COPLANARITY

INTEGRATED CIRCUIT PACKAGE HAVING IMPROVED COPLANARITY

MICROELECTRONIC PACKAGE WITH STRESS-TOLERANT SOLDER BUMP PATTERN

STIFFENING ELECTRONIC PACKAGES

INTEGRATED CIRCUIT PACKAGE WITH A CONDUCTIVE GRID FORMED IN A PACKA...

PACKAGING SUBSTRATE THAT HAS ELECTROPLATED PADS THAT ARE FREE OF PL...

SELECTIVE WETTING PROCESS TO INCREASE SOLDER JOINT STANDOFF

PROCESS FOR MANUFACTURING A PRINTED CIRCUIT BOARD HAVING HIGH DENSI...

ABSORBING EXCESS UNDER-FILL FLOW WITH A SOLDER TRENCH

LOW-PROFILE CHIP PACKAGE WITH MODIFIED HEAT SPREADER

VARIABLE-SIZE SOLDER BUMP STRUCTURES FOR INTEGRATED CIRCUIT PACKAGING

OFFSET INTEGRATED CIRCUIT PACKAGING INTERCONNECTS

SUBSTRATE BUILD UP LAYER TO ACHIEVE BOTH FINER DESIGN RULE AND BETT...

OPEN SOLDER MASK AND OR DIELECTRIC TO INCREASE LID OR RING THICKNES...

NON-SOLDER MASK DEFINED COPPER PAD AND EMBEDDED COPPER PAD TO REDUC...

REDUCED INTEGRATED CIRCUIT PACKAGE LID HEIGHT

PACKAGING SUBSTRATE WITH RELIABLE VIA STRUCTURE

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PREPARING A SUBSTR...

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CONTROLLING WARPIN...

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR AFFIXING A POST TO...

LEAD-FREE STRUCTURES IN A SEMICONDUCTOR DEVICE

BARRIER LAYER TO PREVENT CONDUCTIVE ANODIC FILAMENTS

Contact pad and method of forming a contact pad for an integrated c...

Solder ball assembly for a semiconductor device and method of fabri...