Leocadio Morona Alabin

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor package system with patterned mask over thermal relief
- Patent number 8,274,145
- Issue date Sep 25, 2012
- Stats Chippac Ltd.
- Leocadio M. Alabin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolated stacked die semiconductor packages
- Patent number 8,198,132
- Issue date Jun 12, 2012
- Fairchild Semiconductor Corporation
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Folded lands and vias for multichip semiconductor packages
- Patent number 8,072,051
- Issue date Dec 6, 2011
- Fairchild Semiconductor Corporation
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolated stacked die semiconductor packages
- Patent number 8,053,883
- Issue date Nov 8, 2011
- Fairchild Semiconductor Corporation
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multichip discrete package
- Patent number 7,977,776
- Issue date Jul 12, 2011
- Fairchild Semiconductor Corporation
- Manolito Fabres Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor system-in-package and method for making the same
- Patent number 7,960,211
- Issue date Jun 14, 2011
- Fairchild Semiconductor Corporation
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leadframe-based chip scale semiconductor packages
- Patent number 7,944,031
- Issue date May 17, 2011
- Fairchild Semiconductor Corporation
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor system-in-a-package containing micro-layered lead frame
- Patent number 7,923,847
- Issue date Apr 12, 2011
- Fairchild Semiconductor Corporation
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micro-layered lead frame semiconductor packages
- Patent number 7,888,781
- Issue date Feb 15, 2011
- Fairchild Semiconductor Corporation
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip semiconductor package
- Patent number 7,846,773
- Issue date Dec 7, 2010
- Fairchild Semiconductor Corporation
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip discrete devices in semiconductor packages
- Patent number 7,843,048
- Issue date Nov 30, 2010
- Fairchild Semiconductor Corporation
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit leadless package system
- Patent number 7,498,665
- Issue date Mar 3, 2009
- Stats Chippac Ltd.
- Leocadio M. Alabin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
ISOLATED STACKED DIE SEMICONDUCTOR PACKAGES
- Publication number 20120015482
- Publication date Jan 19, 2012
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGES WITH EMBEDDED HEAT SINK
- Publication number 20110163428
- Publication date Jul 7, 2011
- Manolito Fabres Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FOLDED LANDS AND VIAS FOR MULTICHIP SEMICONDUCTOR PACKAGES
- Publication number 20110062568
- Publication date Mar 17, 2011
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ISOLATED STACKED DIE SEMICONDUCTOR PACKAGES
- Publication number 20110062570
- Publication date Mar 17, 2011
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP SEMICONDUCTOR PACKAGE
- Publication number 20100308461
- Publication date Dec 9, 2010
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PIN DENSITY SEMICONDUCTOR SYSTEM-IN-A-PACKAGE
- Publication number 20100276793
- Publication date Nov 4, 2010
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTICHIP DISCRETE PACKAGE
- Publication number 20100244211
- Publication date Sep 30, 2010
- Manolito Fabres Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-Chip Semiconductor Package
- Publication number 20100181660
- Publication date Jul 22, 2010
- Monolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED CHIP, MICRO-LAYERED LEAD FRAME SEMICONDUCTOR PACKAGE
- Publication number 20100140773
- Publication date Jun 10, 2010
- Manolito Fabres Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL CHIP SCALE SEMICONDUCTOR PACKAGES
- Publication number 20100127375
- Publication date May 27, 2010
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICRO-LAYERED LEAD FRAME SEMICONDUCTOR PACKAGES
- Publication number 20100052118
- Publication date Mar 4, 2010
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR SYSTEM-IN-A-PACKAGE CONTAINING MICRO-LAYERED LEAD FRAME
- Publication number 20100052121
- Publication date Mar 4, 2010
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR SYSTEM-IN-PACKAGE AND METHOD FOR MAKING THE SAME
- Publication number 20100019363
- Publication date Jan 28, 2010
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ISOLATED STACKED DIE SEMICONDUCTOR PACKAGES
- Publication number 20100019362
- Publication date Jan 28, 2010
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP DISCRETE DEVICES IN SEMICONDUCTOR PACKAGES
- Publication number 20090273067
- Publication date Nov 5, 2009
- Manolito Galera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE SYSTEM WITH PATTERNED MASK OVER THERMAL RELIEF
- Publication number 20090008768
- Publication date Jan 8, 2009
- Leocadio M. Alabin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT LEADLESS PACKAGE SYSTEM
- Publication number 20070108567
- Publication date May 17, 2007
- STATS ChipPAC Ltd.
- Leocadio M. Alabin
- H01 - BASIC ELECTRIC ELEMENTS

Leocadio Morona Alabin

Person

Patents Grantslast 30 patents

Semiconductor package system with patterned mask over thermal relief

Isolated stacked die semiconductor packages

Folded lands and vias for multichip semiconductor packages

Isolated stacked die semiconductor packages

Multichip discrete package

Semiconductor system-in-package and method for making the same

Leadframe-based chip scale semiconductor packages

Semiconductor system-in-a-package containing micro-layered lead frame

Micro-layered lead frame semiconductor packages

Multi-chip semiconductor package

Multi-chip discrete devices in semiconductor packages

Integrated circuit leadless package system

Patents Applicationslast 30 patents

ISOLATED STACKED DIE SEMICONDUCTOR PACKAGES

SEMICONDUCTOR PACKAGES WITH EMBEDDED HEAT SINK

FOLDED LANDS AND VIAS FOR MULTICHIP SEMICONDUCTOR PACKAGES

ISOLATED STACKED DIE SEMICONDUCTOR PACKAGES

MULTI-CHIP SEMICONDUCTOR PACKAGE

HIGH PIN DENSITY SEMICONDUCTOR SYSTEM-IN-A-PACKAGE

MULTICHIP DISCRETE PACKAGE

Multi-Chip Semiconductor Package

STACKED CHIP, MICRO-LAYERED LEAD FRAME SEMICONDUCTOR PACKAGE

WAFER LEVEL CHIP SCALE SEMICONDUCTOR PACKAGES

MICRO-LAYERED LEAD FRAME SEMICONDUCTOR PACKAGES

SEMICONDUCTOR SYSTEM-IN-A-PACKAGE CONTAINING MICRO-LAYERED LEAD FRAME

SEMICONDUCTOR SYSTEM-IN-PACKAGE AND METHOD FOR MAKING THE SAME

ISOLATED STACKED DIE SEMICONDUCTOR PACKAGES

MULTI-CHIP DISCRETE DEVICES IN SEMICONDUCTOR PACKAGES

SEMICONDUCTOR PACKAGE SYSTEM WITH PATTERNED MASK OVER THERMAL RELIEF

INTEGRATED CIRCUIT LEADLESS PACKAGE SYSTEM