Leon Stok

Person

Croton on Hudson, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Circuit layout similarity metric for semiconductor testsite coverage
- Patent number 10,839,133
- Issue date Nov 17, 2020
- International Business Machines Corporation
- Rasit Onur Topaloglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical design system and method
- Patent number 8,473,885
- Issue date Jun 25, 2013
- International Business Machines Corporation
- John M. Cohn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical design system and method
- Patent number 8,219,943
- Issue date Jul 10, 2012
- International Business Machines Corporation
- John M Cohn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical design system and method
- Patent number 7,536,664
- Issue date May 19, 2009
- International Business Machines Corporation
- John M. Cohn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for performing timing closure on VLSI chips in a distributed...
- Patent number 7,178,120
- Issue date Feb 13, 2007
- International Business Machines Corporation
- Nathaniel Hieter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for applying fine-grained transforms during pl...
- Patent number 7,047,163
- Issue date May 16, 2006
- International Business Machines Corporation
- Kanad Chakraborty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CMOS tapered gate and synthesis method
- Patent number 6,966,046
- Issue date Nov 15, 2005
- International Business Machines Corporation
- Brian W. Curran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for preserving regularity during logic synthesis
- Patent number 6,557,159
- Issue date Apr 29, 2003
- International Business Machines Corporation
- Thomas Kutzschebauch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wavefront technology mapping
- Patent number 6,334,205
- Issue date Dec 25, 2001
- International Business Machines Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for logic synthesis employing size independent...
- Patent number 6,167,557
- Issue date Dec 26, 2000
- International Business Machines Corporation
- Prabhakarn N. Kudva
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CIRCUIT LAYOUT SIMILARITY METRIC FOR SEMICONDUCTOR TESTSITE COVERAGE
- Publication number 20200364316
- Publication date Nov 19, 2020
- International Business Machines Corporation
- Rasit Onur Topaloglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHYSICAL DESIGN SYSTEM AND METHOD
- Publication number 20120167029
- Publication date Jun 28, 2012
- International Business Machines Corporation
- John M. Cohn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IPHYSICAL DESIGN SYSTEM AND METHOD
- Publication number 20090204930
- Publication date Aug 13, 2009
- International Business Machines Corporation
- John M. Cohn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Physical design system and method
- Publication number 20060036977
- Publication date Feb 16, 2006
- John M. Cohn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for performing timing closure on VLSI chips in a distributed...
- Publication number 20040133860
- Publication date Jul 8, 2004
- International Business Machines Corporation
- Nathaniel Hieter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CMOS tapered gate and synthesis method
- Publication number 20020157079
- Publication date Oct 24, 2002
- International Business Machines Corporation
- Brian W. Curran
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Circuit layout similarity metric for semiconductor testsite coverage

Physical design system and method

Physical design system and method

Physical design system and method

Method for performing timing closure on VLSI chips in a distributed...

Method and apparatus for applying fine-grained transforms during pl...

CMOS tapered gate and synthesis method

Method for preserving regularity during logic synthesis

Wavefront technology mapping

Method and apparatus for logic synthesis employing size independent...

Patents Applicationslast 30 patents

CIRCUIT LAYOUT SIMILARITY METRIC FOR SEMICONDUCTOR TESTSITE COVERAGE

PHYSICAL DESIGN SYSTEM AND METHOD

IPHYSICAL DESIGN SYSTEM AND METHOD

Physical design system and method

Method for performing timing closure on VLSI chips in a distributed...

CMOS tapered gate and synthesis method