LEONARD P GULER

Person

HILLSBORO, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Gate-all-around integrated circuit structures having depopulated ch...
- Patent number 12,369,393
- Issue date Jul 22, 2025
- Intel Corporation
- Dax M. Crum
Information Patent Grant
Fabrication of gate-all-around integrated circuit structures having...
- Patent number 12,369,392
- Issue date Jul 22, 2025
- Intel Corporation
- Leonard P. Guler
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit structures with backside gate partial cut or tre...
- Patent number 12,364,001
- Issue date Jul 15, 2025
- Intel Corporation
- Leonard P. Guler
Information Patent Grant
Integrated circuit structures having metal gates with tapered plugs
- Patent number 12,364,002
- Issue date Jul 15, 2025
- Intel Corporation
- Mohammad Hasan
Information Patent Grant
Dielectric isolation layer between a nanowire transistor and a subs...
- Patent number 12,349,394
- Issue date Jul 1, 2025
- Intel Corporation
- Bruce E. Beattie
Information Patent Grant
Neighboring gate-all-around integrated circuit structures having di...
- Patent number 12,342,612
- Issue date Jun 24, 2025
- Intel Corporation
- Leonard P. Guler
Information Patent Grant
Cavity spacer for nanowire transistors
- Patent number 12,328,905
- Issue date Jun 10, 2025
- Intel Corporation
- William Hsu
Information Patent Grant
Selective growth self-aligned gate endcap (SAGE) architectures with...
- Patent number 12,272,688
- Issue date Apr 8, 2025
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structures having dielectric anchor void
- Patent number 12,266,708
- Issue date Apr 1, 2025
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical edge blocking (VEB) technique for increasing patterning pr...
- Patent number 12,249,541
- Issue date Mar 11, 2025
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architectures with gate-all-around...
- Patent number 12,224,350
- Issue date Feb 11, 2025
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having oxide sub-fins
- Patent number 12,211,925
- Issue date Jan 28, 2025
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self aligned gratings for tight pitch interconnects and methods of...
- Patent number 12,131,991
- Issue date Oct 29, 2024
- Intel Corporation
- Manish Chandhok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical metal splitting using helmets and wrap-around dielectric s...
- Patent number 12,131,989
- Issue date Oct 29, 2024
- Intel Corporation
- Leonard P. Guler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Contact over active gate structures with metal oxide layers to inhi...
- Patent number 12,080,639
- Issue date Sep 3, 2024
- Intel Corporation
- Rami Hourani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of gate-all-around integrated circuit structures having...
- Patent number 12,068,314
- Issue date Aug 20, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architectures with gate-all-around...
- Patent number 12,057,491
- Issue date Aug 6, 2024
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhanced grating aligned patterning for EUV direct print processes
- Patent number 12,051,623
- Issue date Jul 30, 2024
- Intel Corporation
- Seyedhamed M Barghi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plug and recess process for dual metal gate on stacked nanoribbon d...
- Patent number 12,046,652
- Issue date Jul 23, 2024
- Intel Corporation
- Nicole Thomas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated nanowire and nanoribbon patterning in transistor manufac...
- Patent number 12,014,959
- Issue date Jun 18, 2024
- Intel Corporation
- Leonard P Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having depopulated ch...
- Patent number 12,002,810
- Issue date Jun 4, 2024
- Intel Corporation
- Dax M. Crum
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of gate-all-around integrated circuit structures having...
- Patent number 11,990,472
- Issue date May 21, 2024
- Intel Corporation
- Leonard P. Guler
- G11 - INFORMATION STORAGE
Information Patent Grant
1D vertical edge blocking (VEB) via and plug
- Patent number 11,972,979
- Issue date Apr 30, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cavity spacer for nanowire transistors
- Patent number 11,929,396
- Issue date Mar 12, 2024
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Dielectric isolation layer between a nanowire transistor and a subs...
- Patent number 11,901,458
- Issue date Feb 13, 2024
- Intel Corporation
- Bruce E. Beattie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Neighboring gate-all-around integrated circuit structures having di...
- Patent number 11,862,635
- Issue date Jan 2, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architectures with gate-all-around...
- Patent number 11,855,223
- Issue date Dec 26, 2023
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FIN shaping using templates and integrated circuit structures resul...
- Patent number 11,749,733
- Issue date Sep 5, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having oxide sub-fins
- Patent number 11,742,410
- Issue date Aug 29, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
1D vertical edge blocking (VEB) via and plug
- Patent number 11,721,580
- Issue date Aug 8, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING FIN ISOLATION REGIONS BOUND BY...
- Publication number 20250227960
- Publication date Jul 10, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH BACKSIDE GATE PARTIAL CUT OR TRE...
- Publication number 20250227991
- Publication date Jul 10, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH FRONT-SIDE-GUIDED BACKSIDE SOURCE...
- Publication number 20250228008
- Publication date Jul 10, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH BACKSIDE SELF-ALIGNED PENETRATIN...
- Publication number 20250227978
- Publication date Jul 10, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING UNIFORM GRID METAL GATE AND TR...
- Publication number 20250221019
- Publication date Jul 3, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH FRONT-SIDE-CUT BACKSIDE SOURCE OR...
- Publication number 20250221040
- Publication date Jul 3, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH FRONT-SIDE-GUIDED BACKSIDE SOURCE...
- Publication number 20250221041
- Publication date Jul 3, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING LINKS FOR UNIFORM GRID METAL G...
- Publication number 20250220967
- Publication date Jul 3, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE CONTACT EXTENSION
- Publication number 20250221023
- Publication date Jul 3, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
FRONT SIDE AND BACKSIDE SOURCE OR DRAIN CONTACTS
- Publication number 20250220959
- Publication date Jul 3, 2025
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING UNIFORM GRID METAL GATE AND TR...
- Publication number 20250220965
- Publication date Jul 3, 2025
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING DIRECT-ASSEMBLED LINKS FOR UNI...
- Publication number 20250220968
- Publication date Jul 3, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING METAL GATE AND TRENCH CONTACT...
- Publication number 20250212450
- Publication date Jun 26, 2025
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE SELF-ALIGNED BACKBONE FOR FORKSHEET TRANSISTORS
- Publication number 20250204042
- Publication date Jun 19, 2025
- Intel Corporation
- Sukru YEMENICIOGLU
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH VARIED SUB-FIN TRENCHES AND EPITA...
- Publication number 20250204029
- Publication date Jun 19, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING UNIFORM GRID METAL GATE AND TR...
- Publication number 20250203905
- Publication date Jun 19, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH CO-METALIZED ELECTRICAL CONTACT
- Publication number 20250204000
- Publication date Jun 19, 2025
- Intel Corporation
- Kan Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE GROWTH SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH...
- Publication number 20250204032
- Publication date Jun 19, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
UNIAXIAL DUAL STRAIN IN RIBBONIZED CHANNEL
- Publication number 20250194223
- Publication date Jun 12, 2025
- Intel Corporation
- Dan S. Lavric
Information Patent Application
FIN TRIM PLUG STRUCTURES HAVING AN OXIDATION CATALYST LAYER SURROUN...
- Publication number 20250176225
- Publication date May 29, 2025
- Intel Corporation
- Leonard GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING UNIFORM GRID METAL GATE AND TR...
- Publication number 20250176153
- Publication date May 29, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH VARIED INTERNAL SPACERS AND EPITA...
- Publication number 20250151344
- Publication date May 8, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH VARIED EPITAXIAL SOURCE OR DRAIN...
- Publication number 20250151343
- Publication date May 8, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH VARIED ETCH-STOP FOR EPITAXIAL SO...
- Publication number 20250151379
- Publication date May 8, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING CUT METAL GATES
- Publication number 20250133821
- Publication date Apr 24, 2025
- Intel Corporation
- Tahir GHANI
Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND...
- Publication number 20250126832
- Publication date Apr 17, 2025
- Intel Corporation
- Biswajeet GUHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING OXIDE SUB-FINS
- Publication number 20250120152
- Publication date Apr 10, 2025
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE SOURCE/DRAIN TRANSISTOR CONTACT FLOW WITH SELECTIVE ETCH M...
- Publication number 20250113580
- Publication date Apr 3, 2025
- Intel Corporation
- Leonard Guler
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING FIN CUTS
- Publication number 20250113529
- Publication date Apr 3, 2025
- Intel Corporation
- Leonard P. GULER
Information Patent Application
STACKED NANOWIRE TRANSISTOR STRUCTURES WITH ISOLATION REGIONS BOUND...
- Publication number 20250113563
- Publication date Apr 3, 2025
- Intel Corporation
- Leonard Guler

LEONARD P GULER

Person

Patents Grantslast 30 patents

Gate-all-around integrated circuit structures having depopulated ch...

Fabrication of gate-all-around integrated circuit structures having...

Integrated circuit structures with backside gate partial cut or tre...

Integrated circuit structures having metal gates with tapered plugs

Dielectric isolation layer between a nanowire transistor and a subs...

Neighboring gate-all-around integrated circuit structures having di...

Cavity spacer for nanowire transistors

Selective growth self-aligned gate endcap (SAGE) architectures with...

Integrated circuit structures having dielectric anchor void

Vertical edge blocking (VEB) technique for increasing patterning pr...

Self-aligned gate endcap (SAGE) architectures with gate-all-around...

Gate-all-around integrated circuit structures having oxide sub-fins

Self aligned gratings for tight pitch interconnects and methods of...

Vertical metal splitting using helmets and wrap-around dielectric s...

Contact over active gate structures with metal oxide layers to inhi...

Fabrication of gate-all-around integrated circuit structures having...

Self-aligned gate endcap (SAGE) architectures with gate-all-around...

Enhanced grating aligned patterning for EUV direct print processes

Plug and recess process for dual metal gate on stacked nanoribbon d...

Integrated nanowire and nanoribbon patterning in transistor manufac...

Gate-all-around integrated circuit structures having depopulated ch...

Fabrication of gate-all-around integrated circuit structures having...

1D vertical edge blocking (VEB) via and plug

Cavity spacer for nanowire transistors

Dielectric isolation layer between a nanowire transistor and a subs...

Neighboring gate-all-around integrated circuit structures having di...

Self-aligned gate endcap (SAGE) architectures with gate-all-around...

FIN shaping using templates and integrated circuit structures resul...

Gate-all-around integrated circuit structures having oxide sub-fins

1D vertical edge blocking (VEB) via and plug

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT STRUCTURES HAVING FIN ISOLATION REGIONS BOUND BY...

INTEGRATED CIRCUIT STRUCTURES WITH BACKSIDE GATE PARTIAL CUT OR TRE...

INTEGRATED CIRCUIT STRUCTURE WITH FRONT-SIDE-GUIDED BACKSIDE SOURCE...

INTEGRATED CIRCUIT STRUCTURES WITH BACKSIDE SELF-ALIGNED PENETRATIN...

INTEGRATED CIRCUIT STRUCTURES HAVING UNIFORM GRID METAL GATE AND TR...

INTEGRATED CIRCUIT STRUCTURE WITH FRONT-SIDE-CUT BACKSIDE SOURCE OR...

INTEGRATED CIRCUIT STRUCTURE WITH FRONT-SIDE-GUIDED BACKSIDE SOURCE...

INTEGRATED CIRCUIT STRUCTURES HAVING LINKS FOR UNIFORM GRID METAL G...

INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE CONTACT EXTENSION

FRONT SIDE AND BACKSIDE SOURCE OR DRAIN CONTACTS

INTEGRATED CIRCUIT STRUCTURES HAVING UNIFORM GRID METAL GATE AND TR...

INTEGRATED CIRCUIT STRUCTURES HAVING DIRECT-ASSEMBLED LINKS FOR UNI...

INTEGRATED CIRCUIT STRUCTURES HAVING METAL GATE AND TRENCH CONTACT...

BACKSIDE SELF-ALIGNED BACKBONE FOR FORKSHEET TRANSISTORS

INTEGRATED CIRCUIT STRUCTURE WITH VARIED SUB-FIN TRENCHES AND EPITA...

INTEGRATED CIRCUIT STRUCTURES HAVING UNIFORM GRID METAL GATE AND TR...

INTEGRATED CIRCUIT DEVICE WITH CO-METALIZED ELECTRICAL CONTACT

SELECTIVE GROWTH SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH...

UNIAXIAL DUAL STRAIN IN RIBBONIZED CHANNEL

FIN TRIM PLUG STRUCTURES HAVING AN OXIDATION CATALYST LAYER SURROUN...

INTEGRATED CIRCUIT STRUCTURES HAVING UNIFORM GRID METAL GATE AND TR...

INTEGRATED CIRCUIT STRUCTURE WITH VARIED INTERNAL SPACERS AND EPITA...

INTEGRATED CIRCUIT STRUCTURE WITH VARIED EPITAXIAL SOURCE OR DRAIN...

INTEGRATED CIRCUIT STRUCTURE WITH VARIED ETCH-STOP FOR EPITAXIAL SO...

INTEGRATED CIRCUIT STRUCTURES HAVING CUT METAL GATES

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING OXIDE SUB-FINS

BACKSIDE SOURCE/DRAIN TRANSISTOR CONTACT FLOW WITH SELECTIVE ETCH M...

INTEGRATED CIRCUIT STRUCTURES HAVING FIN CUTS

STACKED NANOWIRE TRANSISTOR STRUCTURES WITH ISOLATION REGIONS BOUND...