LEONARD P GULER

Person

HILLSBORO, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Self aligned gratings for tight pitch interconnects and methods of...
- Patent number 12,131,991
- Issue date Oct 29, 2024
- Intel Corporation
- Manish Chandhok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical metal splitting using helmets and wrap-around dielectric s...
- Patent number 12,131,989
- Issue date Oct 29, 2024
- Intel Corporation
- Leonard P. Guler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Contact over active gate structures with metal oxide layers to inhi...
- Patent number 12,080,639
- Issue date Sep 3, 2024
- Intel Corporation
- Rami Hourani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of gate-all-around integrated circuit structures having...
- Patent number 12,068,314
- Issue date Aug 20, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architectures with gate-all-around...
- Patent number 12,057,491
- Issue date Aug 6, 2024
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhanced grating aligned patterning for EUV direct print processes
- Patent number 12,051,623
- Issue date Jul 30, 2024
- Intel Corporation
- Seyedhamed M Barghi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plug and recess process for dual metal gate on stacked nanoribbon d...
- Patent number 12,046,652
- Issue date Jul 23, 2024
- Intel Corporation
- Nicole Thomas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated nanowire and nanoribbon patterning in transistor manufac...
- Patent number 12,014,959
- Issue date Jun 18, 2024
- Intel Corporation
- Leonard P Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having depopulated ch...
- Patent number 12,002,810
- Issue date Jun 4, 2024
- Intel Corporation
- Dax M. Crum
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of gate-all-around integrated circuit structures having...
- Patent number 11,990,472
- Issue date May 21, 2024
- Intel Corporation
- Leonard P. Guler
- G11 - INFORMATION STORAGE
Information Patent Grant
1D vertical edge blocking (VEB) via and plug
- Patent number 11,972,979
- Issue date Apr 30, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cavity spacer for nanowire transistors
- Patent number 11,929,396
- Issue date Mar 12, 2024
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Dielectric isolation layer between a nanowire transistor and a subs...
- Patent number 11,901,458
- Issue date Feb 13, 2024
- Intel Corporation
- Bruce E. Beattie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Neighboring gate-all-around integrated circuit structures having di...
- Patent number 11,862,635
- Issue date Jan 2, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architectures with gate-all-around...
- Patent number 11,855,223
- Issue date Dec 26, 2023
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FIN shaping using templates and integrated circuit structures resul...
- Patent number 11,749,733
- Issue date Sep 5, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having oxide sub-fins
- Patent number 11,742,410
- Issue date Aug 29, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
1D vertical edge blocking (VEB) via and plug
- Patent number 11,721,580
- Issue date Aug 8, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architectures with gate-all-around...
- Patent number 11,715,775
- Issue date Aug 1, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical edge blocking (VEB) technique for increasing patterning pr...
- Patent number 11,594,448
- Issue date Feb 28, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having fin stack isol...
- Patent number 11,594,637
- Issue date Feb 28, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate edge trigate and finFET devices
- Patent number 11,581,315
- Issue date Feb 14, 2023
- Intel Corporation
- Szuya S. Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DEPOP using cyclic selective spacer etch
- Patent number 11,569,370
- Issue date Jan 31, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-planar transistors with channel regions having varying widths
- Patent number 11,569,231
- Issue date Jan 31, 2023
- Intel Corporation
- Stephen D Snyder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin trim plug structures having an oxidation catalyst layer surroun...
- Patent number 11,538,937
- Issue date Dec 27, 2022
- Intel Corporation
- Leonard Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via and plug architectures for integrated circuit interconnects and...
- Patent number 11,527,433
- Issue date Dec 13, 2022
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectric isolation layer between a nanowire transistor and a subs...
- Patent number 11,404,578
- Issue date Aug 2, 2022
- Intel Corporation
- Bruce E. Beattie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Neighboring gate-all-around integrated circuit structures having di...
- Patent number 11,398,474
- Issue date Jul 26, 2022
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architectures with gate-all-around...
- Patent number 11,355,608
- Issue date Jun 7, 2022
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cavity spacer for nanowire transistors
- Patent number 11,342,411
- Issue date May 24, 2022
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY

Patents Applicationslast 30 patents

Information Patent Application
STACKED CMOS TRANSISTOR STRUCTURES WITH COMPLEMENTARY CHANNEL MATER...
- Publication number 20250006737
- Publication date Jan 2, 2025
- Intel Corporation
- Aryan Navabi-Shirazi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE SOURCE OR DRAIN CONTACT...
- Publication number 20250006740
- Publication date Jan 2, 2025
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING REDUCED END CAP
- Publication number 20250006787
- Publication date Jan 2, 2025
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH INTERNAL SPACER LINERS
- Publication number 20250006808
- Publication date Jan 2, 2025
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE LINES HAVING CONDUCTIVE METAL LINER FOR ADVANCED INTEGRA...
- Publication number 20250006628
- Publication date Jan 2, 2025
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR ISOLATION
- Publication number 20240429125
- Publication date Dec 26, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORKSHEET DEVICES WITH DIELECTRIC SPINE AT CELL BOUNDARY
- Publication number 20240429276
- Publication date Dec 26, 2024
- Intel Corporation
- Sukru Yemenicioglu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRENCH CONNECTION OVER DISCONNECTED EPITAXIAL STRUCTURE USING DIREC...
- Publication number 20240421201
- Publication date Dec 19, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED VIA PATTERNING FOR BACKSIDE INTERCONNECTS
- Publication number 20240404917
- Publication date Dec 5, 2024
- Intel Corporation
- Sikandar Abbas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH PARTIAL CHANNEL CAP REMOVAL
- Publication number 20240395886
- Publication date Nov 28, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING METAL-CONTAINING FIN ISOLATION...
- Publication number 20240395815
- Publication date Nov 28, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...
- Publication number 20240363628
- Publication date Oct 31, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE CONDUCTIVE STRUCTURES EXTENDING THROUGH INTEGRATED CIRCUIT...
- Publication number 20240355915
- Publication date Oct 24, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE BRIDGE THROUGH DIELECTRIC WALL BETWEEN SOURCE OR DRAIN C...
- Publication number 20240355890
- Publication date Oct 24, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE BRIDGE THROUGH DIELECTRIC WALL BETWEEN SOURCE OR DRAIN C...
- Publication number 20240355891
- Publication date Oct 24, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND...
- Publication number 20240355903
- Publication date Oct 24, 2024
- Intel Corporation
- Biswajeet GUHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING CUT METAL GATES
- Publication number 20240347539
- Publication date Oct 17, 2024
- Intel Corporation
- Tahir GHANI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Cavity Spacer for Nanowire Transistors
- Publication number 20240347595
- Publication date Oct 17, 2024
- Intel Corporation
- William Hsu
- B82 - NANO-TECHNOLOGY
Information Patent Application
PLUG AND RECESS PROCESS FOR DUAL METAL GATE ON STACKED NANORIBBON D...
- Publication number 20240332389
- Publication date Oct 3, 2024
- Intel Corporation
- Nicole THOMAS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR WITH CHANNEL-SYMMETRIC GATE
- Publication number 20240332290
- Publication date Oct 3, 2024
- Intel Corporation
- Shao-Ming Koh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONSTRAINED EPITAXIAL FORMATION USING DIELECTRIC WALLS
- Publication number 20240321892
- Publication date Sep 26, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE LINK ACROSS GATE CUT IN SEMICONDUCTOR DEVICES
- Publication number 20240321872
- Publication date Sep 26, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES BETWEEN GATE CUTS AND DEEP BACKSIDE VIAS
- Publication number 20240321685
- Publication date Sep 26, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ISOLATED BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES
- Publication number 20240321737
- Publication date Sep 26, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BRIDGING CONTACT STRUCTURES
- Publication number 20240321738
- Publication date Sep 26, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT EXTENDED OVER AN ADJACENT SOURCE OR DRAIN REGION
- Publication number 20240321978
- Publication date Sep 26, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING SELF-ALIGNED UNIFORM GRID META...
- Publication number 20240312986
- Publication date Sep 19, 2024
- Intel Corporation
- Dan S. LAVRIC
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...
- Publication number 20240266353
- Publication date Aug 8, 2024
- Intel Corporation
- Dax M. CRUM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND...
- Publication number 20240243203
- Publication date Jul 18, 2024
- Intel Corporation
- Biswajeet GUHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS TO REDUCE EXTREME ULTRAVIOLET LIGHT FOR PHOTO...
- Publication number 20240241446
- Publication date Jul 18, 2024
- Intel Corporation
- Marvin Paik
- H01 - BASIC ELECTRIC ELEMENTS

LEONARD P GULER

Person

Patents Grantslast 30 patents

Self aligned gratings for tight pitch interconnects and methods of...

Vertical metal splitting using helmets and wrap-around dielectric s...

Contact over active gate structures with metal oxide layers to inhi...

Fabrication of gate-all-around integrated circuit structures having...

Self-aligned gate endcap (SAGE) architectures with gate-all-around...

Enhanced grating aligned patterning for EUV direct print processes

Plug and recess process for dual metal gate on stacked nanoribbon d...

Integrated nanowire and nanoribbon patterning in transistor manufac...

Gate-all-around integrated circuit structures having depopulated ch...

Fabrication of gate-all-around integrated circuit structures having...

1D vertical edge blocking (VEB) via and plug

Cavity spacer for nanowire transistors

Dielectric isolation layer between a nanowire transistor and a subs...

Neighboring gate-all-around integrated circuit structures having di...

Self-aligned gate endcap (SAGE) architectures with gate-all-around...

FIN shaping using templates and integrated circuit structures resul...

Gate-all-around integrated circuit structures having oxide sub-fins

1D vertical edge blocking (VEB) via and plug

Self-aligned gate endcap (SAGE) architectures with gate-all-around...

Vertical edge blocking (VEB) technique for increasing patterning pr...

Gate-all-around integrated circuit structures having fin stack isol...

Self-aligned gate edge trigate and finFET devices

DEPOP using cyclic selective spacer etch

Non-planar transistors with channel regions having varying widths

Fin trim plug structures having an oxidation catalyst layer surroun...

Via and plug architectures for integrated circuit interconnects and...

Dielectric isolation layer between a nanowire transistor and a subs...

Neighboring gate-all-around integrated circuit structures having di...

Self-aligned gate endcap (SAGE) architectures with gate-all-around...

Cavity spacer for nanowire transistors

Patents Applicationslast 30 patents

STACKED CMOS TRANSISTOR STRUCTURES WITH COMPLEMENTARY CHANNEL MATER...

INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE SOURCE OR DRAIN CONTACT...

INTEGRATED CIRCUIT STRUCTURES HAVING REDUCED END CAP

INTEGRATED CIRCUIT STRUCTURES WITH INTERNAL SPACER LINERS

CONDUCTIVE LINES HAVING CONDUCTIVE METAL LINER FOR ADVANCED INTEGRA...

INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR ISOLATION

FORKSHEET DEVICES WITH DIELECTRIC SPINE AT CELL BOUNDARY

TRENCH CONNECTION OVER DISCONNECTED EPITAXIAL STRUCTURE USING DIREC...

SELF-ALIGNED VIA PATTERNING FOR BACKSIDE INTERCONNECTS

INTEGRATED CIRCUIT STRUCTURES WITH PARTIAL CHANNEL CAP REMOVAL

INTEGRATED CIRCUIT STRUCTURES HAVING METAL-CONTAINING FIN ISOLATION...

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...

BACKSIDE CONDUCTIVE STRUCTURES EXTENDING THROUGH INTEGRATED CIRCUIT...

CONDUCTIVE BRIDGE THROUGH DIELECTRIC WALL BETWEEN SOURCE OR DRAIN C...

CONDUCTIVE BRIDGE THROUGH DIELECTRIC WALL BETWEEN SOURCE OR DRAIN C...

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND...

INTEGRATED CIRCUIT STRUCTURES HAVING CUT METAL GATES

Cavity Spacer for Nanowire Transistors

PLUG AND RECESS PROCESS FOR DUAL METAL GATE ON STACKED NANORIBBON D...

TRANSISTOR WITH CHANNEL-SYMMETRIC GATE

CONSTRAINED EPITAXIAL FORMATION USING DIELECTRIC WALLS

GATE LINK ACROSS GATE CUT IN SEMICONDUCTOR DEVICES

SEMICONDUCTOR DEVICES BETWEEN GATE CUTS AND DEEP BACKSIDE VIAS

ISOLATED BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES

BRIDGING CONTACT STRUCTURES

CONTACT EXTENDED OVER AN ADJACENT SOURCE OR DRAIN REGION

INTEGRATED CIRCUIT STRUCTURES HAVING SELF-ALIGNED UNIFORM GRID META...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND...

METHODS AND APPARATUS TO REDUCE EXTREME ULTRAVIOLET LIGHT FOR PHOTO...