Lester Chang

Person

Hsinchu City, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit layout generation method and system
- Patent number 12,135,930
- Issue date Nov 5, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ke-Ying Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit layout generation method and system
- Patent number 11,842,135
- Issue date Dec 12, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ke-Ying Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for integrated circuit design with on-chip variat...
- Patent number 10,860,769
- Issue date Dec 8, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Katherine Chiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit modeling methods and systems
- Patent number 10,846,456
- Issue date Nov 24, 2020
- Taiwan Semiconductor Manufacturing Company Ltd.
- Ke-Ying Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit layout generation method and system
- Patent number 10,796,059
- Issue date Oct 6, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ke-Ying Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for integrated circuit design with on-chip variat...
- Patent number 10,521,538
- Issue date Dec 31, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Katherine Chiang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM
- Publication number 20240386181
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ke-Ying SU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM
- Publication number 20240111935
- Publication date Apr 4, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ke-Ying SU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM
- Publication number 20210019467
- Publication date Jan 21, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ke-Ying SU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Integrated Circuit Design With On-Chip Variat...
- Publication number 20200125782
- Publication date Apr 23, 2020
- Taiwan Semiconductor Manufacturing Co., LTD
- Katherine Chiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT MODELING METHODS AND SYSTEMS
- Publication number 20190340328
- Publication date Nov 7, 2019
- Taiwan Semiconductor Manufacturing company Ltd.
- Ke-Ying SU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM
- Publication number 20190294750
- Publication date Sep 26, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ke-Ying SU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Integrated Circuit Design With On-Chip Variat...
- Publication number 20170316138
- Publication date Nov 2, 2017
- Taiwan Semiconductor Manufacturing Co., LTD
- Katherine Chiang
- G06 - COMPUTING CALCULATING COUNTING

Lester Chang

Person

Patents Grantslast 30 patents

Integrated circuit layout generation method and system

Integrated circuit layout generation method and system

Method and system for integrated circuit design with on-chip variat...

Integrated circuit modeling methods and systems

Integrated circuit layout generation method and system

Method and system for integrated circuit design with on-chip variat...

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM

INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM

INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM

Method and System for Integrated Circuit Design With On-Chip Variat...

INTEGRATED CIRCUIT MODELING METHODS AND SYSTEMS

INTEGRATED CIRCUIT LAYOUT GENERATION METHOD AND SYSTEM

Method and System for Integrated Circuit Design With On-Chip Variat...