Lester M. CRUDELE

Person

Tomball, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
MRAM access coordination systems and methods via pipeline in parallel
- Patent number 11,941,299
- Issue date Mar 26, 2024
- Integrated Silicon Solution, (Cayman) Inc.
- Benjamin Louie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit engine for managing memory meta-stability
- Patent number 11,386,010
- Issue date Jul 12, 2022
- Integrated Silicon Solution, (Cayman) Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MRAM access coordination systems and methods with a plurality of pi...
- Patent number 11,334,288
- Issue date May 17, 2022
- Integrated Silicon Solution, (Cayman) Inc.
- Benjamin Louie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error cache segmentation for power reduction
- Patent number 11,151,042
- Issue date Oct 19, 2021
- Integrated Silicon Solution, (Cayman) Inc.
- Benjamin Louie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MRAM noise mitigation for write operations with simultaneous backgr...
- Patent number 11,010,294
- Issue date May 18, 2021
- Spin Memory, Inc.
- Benjamin Louie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MRAM noise mitigation for background operations by delaying verify...
- Patent number 10,990,465
- Issue date Apr 27, 2021
- Spin Memory, Inc.
- Benjamin Louie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory array with horizontal source line and a virtual source line
- Patent number 10,891,997
- Issue date Jan 12, 2021
- Spin Memory, Inc.
- Neal Berger
- G11 - INFORMATION STORAGE
Information Patent Grant
Over-voltage write operation of tunnel magnet-resistance (“TMR”) me...
- Patent number 10,656,994
- Issue date May 19, 2020
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with a plurality of memory banks where each memory ba...
- Patent number 10,628,316
- Issue date Apr 21, 2020
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-port random access memory
- Patent number 10,546,624
- Issue date Jan 28, 2020
- Spin Memory, Inc.
- Mourad El Baraji
- G11 - INFORMATION STORAGE
Information Patent Grant
On-the-fly bit failure detection and bit redundancy remapping techn...
- Patent number 10,529,439
- Issue date Jan 7, 2020
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to...
- Patent number 10,489,245
- Issue date Nov 26, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forcing bits as bad to widen the window between the distributions o...
- Patent number 10,481,976
- Issue date Nov 19, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with a dual Y-multiplexer structure for performing tw...
- Patent number 10,460,781
- Issue date Oct 29, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory instruction pipeline with a pre-read stage for a write opera...
- Patent number 10,446,210
- Issue date Oct 15, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of flushing the contents of a dynamic redundancy register to...
- Patent number 10,437,723
- Issue date Oct 8, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of processing incomplete memory operations in a memory devic...
- Patent number 10,437,491
- Issue date Oct 8, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of reading data from a memory device using multiple levels o...
- Patent number 10,424,393
- Issue date Sep 24, 2019
- Spin Memory, Inc.
- Mourad El Baraji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Perpendicular source and bit lines for an MRAM array
- Patent number 10,395,711
- Issue date Aug 27, 2019
- Spin Memory, Inc.
- Neal Berger
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array with horizontal source line and sacrificial bitline pe...
- Patent number 10,395,712
- Issue date Aug 27, 2019
- Spin Memory, Inc.
- Neal Berger
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device using levels of dynamic redundancy registers for writ...
- Patent number 10,366,775
- Issue date Jul 30, 2019
- Spin Memory, Inc.
- Mourad El Baraji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device with dynamic redundancy registers
- Patent number 10,366,774
- Issue date Jul 30, 2019
- Spin Memory, Inc.
- Mourad El Baraji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of writing contents in memory during a power up sequence usi...
- Patent number 10,360,964
- Issue date Jul 23, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory instruction pipeline with an additional write stage in a mem...
- Patent number 10,192,601
- Issue date Jan 29, 2019
- SPIN TRANSFER TECHNOLOGIES, INC.
- Neal Berger
- G11 - INFORMATION STORAGE
Information Patent Grant
Smart cache design to prevent overflow for a memory device with a d...
- Patent number 10,192,602
- Issue date Jan 29, 2019
- SPIN TRANSFER TECHNOLOGIES, INC.
- Neal Berger
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MRAM ACCESS COORDINATION SYSTEMS AND METHODS
- Publication number 20220276807
- Publication date Sep 1, 2022
- Integrated Silicon Solution, (Cayman) Inc.
- Benjamin LOUIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT ENGINE FOR MANAGING MEMORY META-STABILITY
- Publication number 20210089455
- Publication date Mar 25, 2021
- Spin Memory, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MRAM NOISE MITIGATION FOR BACKGROUND OPERATIONS BY DELAYING VERIFY...
- Publication number 20200057687
- Publication date Feb 20, 2020
- Spin Memory, Inc.
- Benjamin LOUIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MRAM NOISE MITIGATION FOR WRITE OPERATIONS WITH SIMULTANEOUS BACKGR...
- Publication number 20200050545
- Publication date Feb 13, 2020
- Spin Memory, Inc.
- Benjamin LOUIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CACHE SEGMENTATION FOR POWER REDUCTION
- Publication number 20200042450
- Publication date Feb 6, 2020
- Spin Memory, Inc.
- Benjamin LOUIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MRAM ACCESS COORDINATION SYSTEMS AND METHODS
- Publication number 20190303044
- Publication date Oct 3, 2019
- Spin Memory, Inc.
- Benjamin LOUIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERPENDICULAR SOURCE AND BIT LINES FOR AN MRAM ARRAY
- Publication number 20190206470
- Publication date Jul 4, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-PORT RANDOM ACCESS MEMORY
- Publication number 20190206468
- Publication date Jul 4, 2019
- Spin Transfer Technologies, Inc.
- Mourad EL-BARAJI
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY WITH HORIZONTAL SOURCE LINE AND SACRIFICIAL BITLINE PE...
- Publication number 20190206473
- Publication date Jul 4, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY WITH HORIZONTAL SOURCE LINE AND A VIRTUAL SOURCE LINE
- Publication number 20190206471
- Publication date Jul 4, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
ON-THE-FLY BIT FAILURE DETECTION AND BIT REDUNDANCY REMAPPING TECHN...
- Publication number 20190122746
- Publication date Apr 25, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
OVER-VOLTAGE WRITE OPERATION OF TUNNEL MAGNET-RESISTANCE ("TMR") ME...
- Publication number 20190121694
- Publication date Apr 25, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
FORCING BITS AS BAD TO WIDEN THE WINDOW BETWEEN THE DISTRIBUTIONS O...
- Publication number 20190121692
- Publication date Apr 25, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
FORCING STUCK BITS, WATERFALL BITS, SHUNT BITS AND LOW TMR BITS TO...
- Publication number 20190121693
- Publication date Apr 25, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF WRITING CONTENTS IN MEMORY DURING A POWER UP SEQUENCE USI...
- Publication number 20180122447
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY INSTRUCTION PIPELINE WITH A PRE-READ STAGE FOR A WRITE OPERA...
- Publication number 20180122448
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH A PLURALITY OF MEMORY BANKS WHERE EACH MEMORY BA...
- Publication number 20180121361
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF FLUSHING THE CONTENTS OF A DYNAMIC REDUNDANCY REGISTER TO...
- Publication number 20180121355
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY INSTRUCTION PIPELINE WITH AN ADDITIONAL WRITE STAGE IN A MEM...
- Publication number 20180122449
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH A DUAL Y-MULTIPLEXER STRUCTURE FOR PERFORMING TW...
- Publication number 20180122446
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
SMART CACHE DESIGN TO PREVENT OVERFLOW FOR A MEMORY DEVICE WITH A D...
- Publication number 20180122450
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF PROCESSING INCOMPLETED MEMORY OPERATIONS IN A MEMORY DEVI...
- Publication number 20180121117
- Publication date May 3, 2018
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF READING DATA FROM A MEMORY DEVICE USING DYNAMIC REDUNDANC...
- Publication number 20180114589
- Publication date Apr 26, 2018
- Spin Transfer Technologies, Inc.
- Mourad EL BARAJI
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE USING DYNAMIC REDUNDANCY REGISTERS
- Publication number 20180114590
- Publication date Apr 26, 2018
- Spin Transfer Technologies, Inc.
- Mourad EL BARAJI
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE WITH DYNAMIC REDUNDANCY REGISTERS
- Publication number 20180090226
- Publication date Mar 29, 2018
- Spin Transfer Technologies, Inc.
- Mourad EL BARAJI
- G11 - INFORMATION STORAGE

Lester M. CRUDELE

Person

Patents Grantslast 30 patents

MRAM access coordination systems and methods via pipeline in parallel

Circuit engine for managing memory meta-stability

MRAM access coordination systems and methods with a plurality of pi...

Error cache segmentation for power reduction

MRAM noise mitigation for write operations with simultaneous backgr...

MRAM noise mitigation for background operations by delaying verify...

Memory array with horizontal source line and a virtual source line

Over-voltage write operation of tunnel magnet-resistance (“TMR”) me...

Memory device with a plurality of memory banks where each memory ba...

Multi-port random access memory

On-the-fly bit failure detection and bit redundancy remapping techn...

Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to...

Forcing bits as bad to widen the window between the distributions o...

Memory device with a dual Y-multiplexer structure for performing tw...

Memory instruction pipeline with a pre-read stage for a write opera...

Method of flushing the contents of a dynamic redundancy register to...

Method of processing incomplete memory operations in a memory devic...

Method of reading data from a memory device using multiple levels o...

Perpendicular source and bit lines for an MRAM array

Memory array with horizontal source line and sacrificial bitline pe...

Memory device using levels of dynamic redundancy registers for writ...

Device with dynamic redundancy registers

Method of writing contents in memory during a power up sequence usi...

Memory instruction pipeline with an additional write stage in a mem...

Smart cache design to prevent overflow for a memory device with a d...

Patents Applicationslast 30 patents

MRAM ACCESS COORDINATION SYSTEMS AND METHODS

CIRCUIT ENGINE FOR MANAGING MEMORY META-STABILITY

MRAM NOISE MITIGATION FOR BACKGROUND OPERATIONS BY DELAYING VERIFY...

MRAM NOISE MITIGATION FOR WRITE OPERATIONS WITH SIMULTANEOUS BACKGR...

ERROR CACHE SEGMENTATION FOR POWER REDUCTION

MRAM ACCESS COORDINATION SYSTEMS AND METHODS

PERPENDICULAR SOURCE AND BIT LINES FOR AN MRAM ARRAY

MULTI-PORT RANDOM ACCESS MEMORY

MEMORY ARRAY WITH HORIZONTAL SOURCE LINE AND SACRIFICIAL BITLINE PE...

MEMORY ARRAY WITH HORIZONTAL SOURCE LINE AND A VIRTUAL SOURCE LINE

ON-THE-FLY BIT FAILURE DETECTION AND BIT REDUNDANCY REMAPPING TECHN...

OVER-VOLTAGE WRITE OPERATION OF TUNNEL MAGNET-RESISTANCE ("TMR") ME...

FORCING BITS AS BAD TO WIDEN THE WINDOW BETWEEN THE DISTRIBUTIONS O...

FORCING STUCK BITS, WATERFALL BITS, SHUNT BITS AND LOW TMR BITS TO...

METHOD OF WRITING CONTENTS IN MEMORY DURING A POWER UP SEQUENCE USI...

MEMORY INSTRUCTION PIPELINE WITH A PRE-READ STAGE FOR A WRITE OPERA...

MEMORY DEVICE WITH A PLURALITY OF MEMORY BANKS WHERE EACH MEMORY BA...

METHOD OF FLUSHING THE CONTENTS OF A DYNAMIC REDUNDANCY REGISTER TO...

MEMORY INSTRUCTION PIPELINE WITH AN ADDITIONAL WRITE STAGE IN A MEM...

MEMORY DEVICE WITH A DUAL Y-MULTIPLEXER STRUCTURE FOR PERFORMING TW...

SMART CACHE DESIGN TO PREVENT OVERFLOW FOR A MEMORY DEVICE WITH A D...

METHOD OF PROCESSING INCOMPLETED MEMORY OPERATIONS IN A MEMORY DEVI...

METHOD OF READING DATA FROM A MEMORY DEVICE USING DYNAMIC REDUNDANC...

MEMORY DEVICE USING DYNAMIC REDUNDANCY REGISTERS

DEVICE WITH DYNAMIC REDUNDANCY REGISTERS