Liang Chen

Person

Allen, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatuses and methods for a per-DRAM addressability synchronizer...
- Patent number 12,183,385
- Issue date Dec 31, 2024
- Micron Technology, Inc.
- William C. Waldrop
- G11 - INFORMATION STORAGE
Information Patent Grant
Command clock gate implementation with chip select signal training...
- Patent number 11,823,729
- Issue date Nov 21, 2023
- Micron Technology, Inc.
- Liang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for centralized address capture circuitry
- Patent number 11,675,541
- Issue date Jun 13, 2023
- Micron Technology, Inc.
- Liang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write leveling a memory device using write DLL circuitry
- Patent number 11,456,031
- Issue date Sep 27, 2022
- Micron Technology, Inc.
- Liang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write leveling a memory device
- Patent number 11,144,241
- Issue date Oct 12, 2021
- Micron Technology, Inc.
- Daniel B. Penney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DFE conditioning for write operations of a memory device
- Patent number 10,825,494
- Issue date Nov 3, 2020
- Micron Technology, Inc.
- Daniel B. Penney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with a signaling mechanism
- Patent number 10,770,116
- Issue date Sep 8, 2020
- Micron Technology
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE
Information Patent Grant
Timing circuit for command path in a memory device
- Patent number 10,679,683
- Issue date Jun 9, 2020
- Micron Technology, Inc.
- Liang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gap detection for consecutive write operations of a memory device
- Patent number 10,672,441
- Issue date Jun 2, 2020
- Micron Technology, Inc.
- Daniel B. Penney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write level initialization synchronization
- Patent number 10,664,173
- Issue date May 26, 2020
- Micron Technology, Inc.
- Gary Howe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing circuit for command path in a memory device
- Patent number 10,607,671
- Issue date Mar 31, 2020
- Micron Technology, Inc.
- Liang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DQS gating in a parallelizer of a memory device
- Patent number 10,535,387
- Issue date Jan 14, 2020
- Micron Technology, Inc.
- Daniel B. Penney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DFE conditioning for write operations of a memory device
- Patent number 10,490,241
- Issue date Nov 26, 2019
- Micron Technology, Inc.
- Daniel B. Penney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write leveling a memory device
- Patent number 10,452,319
- Issue date Oct 22, 2019
- Micron Technology, Inc.
- Daniel B. Penney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with a signaling mechanism
- Patent number 10,373,654
- Issue date Aug 6, 2019
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
APPARATUSES AND METHODS FOR A PER-DRAM ADDRESSABILITY SYNCHRONIZER...
- Publication number 20240062803
- Publication date Feb 22, 2024
- Micron Technology, Inc.
- William C. Waldrop
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS FOR CENTRALIZED ADDRESS CAPTURE CIRCUITRY
- Publication number 20230124182
- Publication date Apr 20, 2023
- Micron Technology, Inc.
- Liang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMAND CLOCK GATE IMPLEMENTATION WITH CHIP SELECT SIGNAL TRAINING...
- Publication number 20230108373
- Publication date Apr 6, 2023
- Micron Technology, Inc.
- Liang Chen
- G11 - INFORMATION STORAGE
Information Patent Application
WRITE LEVELING A MEMORY DEVICE USING WRITE DLL CIRCUITRY
- Publication number 20220180918
- Publication date Jun 9, 2022
- Micron Technology, Inc.
- Liang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DFE CONDITIONING FOR WRITE OPERATIONS OF A MEMORY DEVICE
- Publication number 20200082856
- Publication date Mar 12, 2020
- Micron Technology, Inc.
- Daniel B. Penney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE LEVELING A MEMORY DEVICE
- Publication number 20190391763
- Publication date Dec 26, 2019
- Micron Technology, Inc.
- Daniel B. Penney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH A SIGNALING MECHANISM
- Publication number 20190348081
- Publication date Nov 14, 2019
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DFE CONDITIONING FOR WRITE OPERATIONS OF A MEMORY DEVICE
- Publication number 20190259431
- Publication date Aug 22, 2019
- Micron Technology, Inc.
- Daniel B. Penney
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
GAP DETECTION FOR CONSECUTIVE WRITE OPERATIONS OF A MEMORY DEVICE
- Publication number 20190259433
- Publication date Aug 22, 2019
- Micron Technology, Inc.
- Daniel B. Penney
- G11 - INFORMATION STORAGE
Information Patent Application
TIMING CIRCUIT FOR COMMAND PATH IN A MEMORY DEVICE
- Publication number 20190259442
- Publication date Aug 22, 2019
- Micron Technology, Inc.
- Liang Chen
- G11 - INFORMATION STORAGE
Information Patent Application
DQS GATING IN A PARALLELIZER OF A MEMORY DEVICE
- Publication number 20190244645
- Publication date Aug 8, 2019
- Micron Technology, Inc.
- Daniel B. Penney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE LEVEL INITIALIZATION SYNCRONIZATION
- Publication number 20190235760
- Publication date Aug 1, 2019
- Micron Technology, Inc.
- Gary Howe
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Apparatuses and methods for a per-DRAM addressability synchronizer...

Command clock gate implementation with chip select signal training...

Systems and methods for centralized address capture circuitry

Write leveling a memory device using write DLL circuitry

Write leveling a memory device

DFE conditioning for write operations of a memory device

Memory device with a signaling mechanism

Timing circuit for command path in a memory device

Gap detection for consecutive write operations of a memory device

Write level initialization synchronization

Timing circuit for command path in a memory device

DQS gating in a parallelizer of a memory device

DFE conditioning for write operations of a memory device

Write leveling a memory device

Memory device with a signaling mechanism

Patents Applicationslast 30 patents

APPARATUSES AND METHODS FOR A PER-DRAM ADDRESSABILITY SYNCHRONIZER...

SYSTEMS AND METHODS FOR CENTRALIZED ADDRESS CAPTURE CIRCUITRY

COMMAND CLOCK GATE IMPLEMENTATION WITH CHIP SELECT SIGNAL TRAINING...

WRITE LEVELING A MEMORY DEVICE USING WRITE DLL CIRCUITRY

DFE CONDITIONING FOR WRITE OPERATIONS OF A MEMORY DEVICE

WRITE LEVELING A MEMORY DEVICE

MEMORY DEVICE WITH A SIGNALING MECHANISM

DFE CONDITIONING FOR WRITE OPERATIONS OF A MEMORY DEVICE

GAP DETECTION FOR CONSECUTIVE WRITE OPERATIONS OF A MEMORY DEVICE

TIMING CIRCUIT FOR COMMAND PATH IN A MEMORY DEVICE

DQS GATING IN A PARALLELIZER OF A MEMORY DEVICE

WRITE LEVEL INITIALIZATION SYNCRONIZATION