Liang Ge

Person

Shanghai, CN

People

Patents Grantslast 30 patents

Information Patent Grant
Light hibernation mode for memory
- Patent number 12,164,786
- Issue date Dec 10, 2024
- Micron Technology, Inc.
- Liang Ge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performance tuning for a memory device
- Patent number 12,141,473
- Issue date Nov 12, 2024
- Micron Technology, Inc.
- Liang Ge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Alignment of activation periods
- Patent number 11,977,749
- Issue date May 7, 2024
- Micron Technology, Inc.
- Liang Ge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache allocation techniques
- Patent number 11,822,478
- Issue date Nov 21, 2023
- Micron Technology, Inc.
- Liang Ge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock tree planning for an ASIC
- Patent number 8,793,630
- Issue date Jul 29, 2014
- International Business Machines Corporation
- Liang Ge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constraint optimization of sub-net level routing in asic design
- Patent number 8,543,964
- Issue date Sep 24, 2013
- International Business Machines Corporation
- Liang Ge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for estimating the latency time of a clock tree in an ASIC d...
- Patent number 8,453,085
- Issue date May 28, 2013
- International Business Machines Corporation
- Liang Ge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable direct memory access controller having pipelined and s...
- Patent number 7,984,204
- Issue date Jul 19, 2011
- International Business Machines Corporation
- Adrian S. Butter
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ALIGNMENT OF ACTIVATION PERIODS
- Publication number 20230315307
- Publication date Oct 5, 2023
- Micron Technology, Inc.
- Liang Ge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMANCE TUNING FOR A MEMORY DEVICE
- Publication number 20230205456
- Publication date Jun 29, 2023
- Micron Technology, Inc.
- Liang Ge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE ALLOCATION TECHNIQUES
- Publication number 20230185723
- Publication date Jun 15, 2023
- Micron Technology, Inc.
- Liang Ge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC INTERVAL FOR A MEMORY DEVICE TO ENTER A LOW POWER STATE
- Publication number 20220398024
- Publication date Dec 15, 2022
- Micron Technology, Inc.
- Liang Ge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Tree Planning for an ASIC
- Publication number 20120304136
- Publication date Nov 29, 2012
- International Business Machines Corporation
- Liang Ge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTRAINT OPTIMIZATION OF SUB-NET LEVEL ROUTING IN ASIC DESIGN
- Publication number 20120110541
- Publication date May 3, 2012
- International Business Machines Corporation
- Liang Ge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method For Estimating The Latency Time Of A Clock Tree In An Asic D...
- Publication number 20120047478
- Publication date Feb 23, 2012
- International Business Machines Corporation
- Liang Ge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable Direct Memory Access Controller
- Publication number 20090287860
- Publication date Nov 19, 2009
- Adrian S. Butter
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Light hibernation mode for memory

Performance tuning for a memory device

Alignment of activation periods

Cache allocation techniques

Clock tree planning for an ASIC

Constraint optimization of sub-net level routing in asic design

Method for estimating the latency time of a clock tree in an ASIC d...

Programmable direct memory access controller having pipelined and s...

Patents Applicationslast 30 patents

ALIGNMENT OF ACTIVATION PERIODS

PERFORMANCE TUNING FOR A MEMORY DEVICE

CACHE ALLOCATION TECHNIQUES

DYNAMIC INTERVAL FOR A MEMORY DEVICE TO ENTER A LOW POWER STATE

Clock Tree Planning for an ASIC

CONSTRAINT OPTIMIZATION OF SUB-NET LEVEL ROUTING IN ASIC DESIGN

Method For Estimating The Latency Time Of A Clock Tree In An Asic D...

Programmable Direct Memory Access Controller