Liang-Teck Pang

Person

Albany, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Stitchable global clock for 3D chips
- Patent number 9,800,232
- Issue date Oct 24, 2017
- International Business Machines Corporation
- Robert L. Franch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tunable sector buffer for wide bandwidth resonant global clock dist...
- Patent number 9,612,612
- Issue date Apr 4, 2017
- International Business Machines Corporation
- Thomas J. Bucelot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stitchable global clock for 3D chips
- Patent number 9,348,357
- Issue date May 24, 2016
- International Business Machines Corporation
- Robert L. Franch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed phase detection for clock synchronization in multi-laye...
- Patent number 9,231,603
- Issue date Jan 5, 2016
- International Business Machines Corporation
- Yong Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tunable sector buffer for wide bandwidth resonant global clock dist...
- Patent number 9,058,130
- Issue date Jun 16, 2015
- International Business Machines Corporation
- Thomas J. Bucelot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wide bandwidth resonant global clock distribution
- Patent number 9,054,682
- Issue date Jun 9, 2015
- International Business Machines Corporation
- Thomas J. Bucelot
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit technique to electrically characterize block mask shifts
- Patent number 8,969,104
- Issue date Mar 3, 2015
- International Business Machines Corporation
- Emrah Acar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programming the behavior of individual chips or strata in a 3D stac...
- Patent number 8,928,350
- Issue date Jan 6, 2015
- International Business Machines Corporation
- Liang-Teck Pang
- G01 - MEASURING TESTING
Information Patent Grant
Defect detection on characteristically capacitive circuit nodes
- Patent number 8,860,425
- Issue date Oct 14, 2014
- International Business Machines Corporation
- Liang-Teck Pang
- G01 - MEASURING TESTING
Information Patent Grant
Changing resonant clock modes
- Patent number 8,736,342
- Issue date May 27, 2014
- International Business Machines Corporation
- Thomas J. Bucelot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variable resistance switch for wide bandwidth resonant global clock...
- Patent number 8,704,576
- Issue date Apr 22, 2014
- International Business Machines Corporation
- Thomas J. Bucelot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
AC supply noise reduction in a 3D stack with voltage sensing and cl...
- Patent number 8,587,357
- Issue date Nov 19, 2013
- International Business Machines Corporation
- Jae-Joon Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D chip stack skew reduction with resonant clock and inductive coup...
- Patent number 8,576,000
- Issue date Nov 5, 2013
- International Business Machines Corporation
- Jae-Joon Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Synchronizing global clocks in 3D stacks of integrated circuits by...
- Patent number 8,525,569
- Issue date Sep 3, 2013
- International Business Machines Corporation
- Thomas J. Bucelot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programming the behavior of individual chips or strata in a 3D stac...
- Patent number 8,519,735
- Issue date Aug 27, 2013
- International Business Machines Corporation
- Liang-Teck Pang
- G01 - MEASURING TESTING
Information Patent Grant
3D chip stack skew reduction with resonant clock and inductive coup...
- Patent number 8,466,739
- Issue date Jun 18, 2013
- International Business Machines Corporation
- Jae-Joon Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Optimizing SRAM performance over extended voltage or process range...
- Patent number 7,864,625
- Issue date Jan 4, 2011
- International Business Machines Corporation
- Gary D. Carpenter
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline-to-bitline output timing ring oscillator circuit for evalu...
- Patent number 7,760,565
- Issue date Jul 20, 2010
- International Business Machines Corporation
- Jente B. Kuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Storage array including a local clock buffer with programmable timing
- Patent number 7,668,037
- Issue date Feb 23, 2010
- International Business Machines Corporation
- Gary D. Carpenter
- G11 - INFORMATION STORAGE
Information Patent Grant
Pulsed ring oscillator circuit for storage cell read timing evaluation
- Patent number 7,620,510
- Issue date Nov 17, 2009
- International Business Machines Corporation
- Gary D. Carpenter
- G11 - INFORMATION STORAGE
Information Patent Grant
Pulsed ring oscillator circuit for storage cell read timing evaluation
- Patent number 7,409,305
- Issue date Aug 5, 2008
- International Business Machines Corporation
- Gary D. Carpenter
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
STITCHABLE GLOBAL CLOCK FOR 3D CHIPS
- Publication number 20160211833
- Publication date Jul 21, 2016
- International Business Machines Corporation
- ROBERT L. FRANCH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STITCHABLE GLOBAL CLOCK FOR 3D CHIPS
- Publication number 20150378388
- Publication date Dec 31, 2015
- International Business Machines Corporation
- ROBERT L. FRANCH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED PHASE DETECTION FOR CLOCK SYNCHRONIZATION IN MULTI-LAYE...
- Publication number 20150280722
- Publication date Oct 1, 2015
- International Business Machines Corporation
- Yong Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Dist...
- Publication number 20150234422
- Publication date Aug 20, 2015
- International Business Machines Corporation
- Thomas J. Bucelot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT TECHNIQUE TO ELECTRICALLY CHARACTERIZE BLOCK MASK SHIFTS
- Publication number 20150179536
- Publication date Jun 25, 2015
- International Business Machines Corporation
- Emrah Acar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Dist...
- Publication number 20140223210
- Publication date Aug 7, 2014
- International Business Machines Corporation
- Thomas J. Bucelot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Wide Bandwidth Resonant Global Clock Distribution
- Publication number 20140218087
- Publication date Aug 7, 2014
- International Business Machines Corporation
- Thomas J. Bucelot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHANGING RESONANT CLOCK MODES
- Publication number 20140167832
- Publication date Jun 19, 2014
- International Business Machines Corporation
- Thomas J. Bucelot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT TECHNIQUE TO ELECTRICALLY CHARACTERIZE BLOCK MASK SHIFTS
- Publication number 20130320340
- Publication date Dec 5, 2013
- International Business Machines Corporation
- Emrah Acar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Defect Detection on Characteristically Capacitive Circuit Nodes
- Publication number 20130229189
- Publication date Sep 5, 2013
- International Business Machines Corporation
- Liang-Teck Pang
- G01 - MEASURING TESTING
Information Patent Application
SYNCHRONIZING GLOBAL CLOCKS IN 3D STACKS OF INTEGRATED CIRCUITS BY...
- Publication number 20130049827
- Publication date Feb 28, 2013
- International Business Machines Corporation
- THOMAS J. BUCELOT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AC SUPPLY NOISE REDUCTION IN A 3D STACK WITH VOLTAGE SENSING AND CL...
- Publication number 20130049828
- Publication date Feb 28, 2013
- International Business Machines Corporation
- JAE-JOON KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUP...
- Publication number 20130049824
- Publication date Feb 28, 2013
- International Business Machines Corporation
- JAE-JOON KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMING THE BEHAVIOR OF INDIVIDUAL CHIPS OR STRATA IN A 3D STAC...
- Publication number 20130049795
- Publication date Feb 28, 2013
- International Business Machines Corporation
- LIANG-TECK PANG
- G01 - MEASURING TESTING
Information Patent Application
PROGRAMMING THE BEHAVIOR OF INDIVIDUAL CHIPS OR STRATA IN A 3D STAC...
- Publication number 20130049796
- Publication date Feb 28, 2013
- International Business Machines Corporation
- LIANG-TECK PANG
- G01 - MEASURING TESTING
Information Patent Application
3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUP...
- Publication number 20130049826
- Publication date Feb 28, 2013
- International Business Machines Corporation
- JAE-JOON KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimizing Sram Performance over Extended Voltage or Process Range...
- Publication number 20100085823
- Publication date Apr 8, 2010
- International Business Machines Corporation
- Gary D. Carpenter
- G11 - INFORMATION STORAGE
Information Patent Application
Storage Array Including a Local Clock Buffer with Programmable Timing
- Publication number 20090116312
- Publication date May 7, 2009
- Gary D. Carpenter
- G11 - INFORMATION STORAGE
Information Patent Application
Wordline-To-Bitline Output Timing Ring Oscillator Circuit for Evalu...
- Publication number 20090027065
- Publication date Jan 29, 2009
- Jente B. Kuang
- G01 - MEASURING TESTING
Information Patent Application
PULSED RING OSCILLATOR CIRCUIT FOR STORAGE CELL READ TIMING EVALUATION
- Publication number 20080225615
- Publication date Sep 18, 2008
- Gary D. Carpenter
- G01 - MEASURING TESTING

Liang-Teck Pang

Person

Patents Grantslast 30 patents

Stitchable global clock for 3D chips

Tunable sector buffer for wide bandwidth resonant global clock dist...

Stitchable global clock for 3D chips

Distributed phase detection for clock synchronization in multi-laye...

Tunable sector buffer for wide bandwidth resonant global clock dist...

Wide bandwidth resonant global clock distribution

Circuit technique to electrically characterize block mask shifts

Programming the behavior of individual chips or strata in a 3D stac...

Defect detection on characteristically capacitive circuit nodes

Changing resonant clock modes

Variable resistance switch for wide bandwidth resonant global clock...

AC supply noise reduction in a 3D stack with voltage sensing and cl...

3D chip stack skew reduction with resonant clock and inductive coup...

Synchronizing global clocks in 3D stacks of integrated circuits by...

Programming the behavior of individual chips or strata in a 3D stac...

3D chip stack skew reduction with resonant clock and inductive coup...

Optimizing SRAM performance over extended voltage or process range...

Wordline-to-bitline output timing ring oscillator circuit for evalu...

Storage array including a local clock buffer with programmable timing

Pulsed ring oscillator circuit for storage cell read timing evaluation

Pulsed ring oscillator circuit for storage cell read timing evaluation

Patents Applicationslast 30 patents

STITCHABLE GLOBAL CLOCK FOR 3D CHIPS

STITCHABLE GLOBAL CLOCK FOR 3D CHIPS

DISTRIBUTED PHASE DETECTION FOR CLOCK SYNCHRONIZATION IN MULTI-LAYE...

Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Dist...

CIRCUIT TECHNIQUE TO ELECTRICALLY CHARACTERIZE BLOCK MASK SHIFTS

Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Dist...

Wide Bandwidth Resonant Global Clock Distribution

CHANGING RESONANT CLOCK MODES

CIRCUIT TECHNIQUE TO ELECTRICALLY CHARACTERIZE BLOCK MASK SHIFTS

Defect Detection on Characteristically Capacitive Circuit Nodes

SYNCHRONIZING GLOBAL CLOCKS IN 3D STACKS OF INTEGRATED CIRCUITS BY...

AC SUPPLY NOISE REDUCTION IN A 3D STACK WITH VOLTAGE SENSING AND CL...

3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUP...

PROGRAMMING THE BEHAVIOR OF INDIVIDUAL CHIPS OR STRATA IN A 3D STAC...

PROGRAMMING THE BEHAVIOR OF INDIVIDUAL CHIPS OR STRATA IN A 3D STAC...

3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUP...

Optimizing Sram Performance over Extended Voltage or Process Range...

Storage Array Including a Local Clock Buffer with Programmable Timing

Wordline-To-Bitline Output Timing Ring Oscillator Circuit for Evalu...

PULSED RING OSCILLATOR CIRCUIT FOR STORAGE CELL READ TIMING EVALUATION