Linda Pei Ee Chua

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device and method of forming interposer frame over se...
- Patent number RE48408
- Issue date Jan 26, 2021
- JCET Semiconductor (Shaoxing) Co., Ltd.
- Reza A. Pagaila
Information Patent Grant
Semiconductor device and method of forming interposer frame over se...
- Patent number RE48111
- Issue date Jul 21, 2020
- JCET Semiconductor (Shaoxing) Co. Ltd.
- Reza A. Pagaila
Information Patent Grant
Semiconductor device and method of forming Fo-WLCSP with recessed i...
- Patent number 10,388,584
- Issue date Aug 20, 2019
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming electromagnetic (EM) shi...
- Patent number 10,388,612
- Issue date Aug 20, 2019
- STATS ChipPAC Pte. Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system and method of manufacture thereof
- Patent number 10,043,733
- Issue date Aug 7, 2018
- STATS ChipPAC Pte. Ltd.
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming interposer frame over se...
- Patent number 9,893,045
- Issue date Feb 13, 2018
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming stepped interconnect lay...
- Patent number 9,824,975
- Issue date Nov 21, 2017
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with a grid array with a leadfr...
- Patent number 9,799,589
- Issue date Oct 24, 2017
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming electromagnetic (EM) shi...
- Patent number 9,754,897
- Issue date Sep 5, 2017
- STATS ChipPAC, Pte. Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming cavity adjacent to sensi...
- Patent number 9,679,881
- Issue date Jun 13, 2017
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with unplated leadframe and met...
- Patent number 9,620,480
- Issue date Apr 11, 2017
- STATS ChipPAC Pte. Ltd.
- Garret Dimaculangan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with routable trace and method...
- Patent number 9,576,873
- Issue date Feb 21, 2017
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming interconnect structure a...
- Patent number 9,530,738
- Issue date Dec 27, 2016
- STATS ChipPAC Pte. Ltd.
- Linda Pei Ee Chua
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming base substrate with rece...
- Patent number 9,449,932
- Issue date Sep 20, 2016
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of embedding thermally conductive l...
- Patent number 9,443,828
- Issue date Sep 13, 2016
- STATS ChipPAC Pte. Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming penetrable film encapsul...
- Patent number 9,431,331
- Issue date Aug 30, 2016
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of using substrate with conductive...
- Patent number 9,368,423
- Issue date Jun 14, 2016
- STATS ChipPAC Pte. Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming through vias with reflow...
- Patent number 9,331,002
- Issue date May 3, 2016
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with transferable trace lead frame
- Patent number 9,324,584
- Issue date Apr 26, 2016
- Stats Chippac Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with external interconnect and...
- Patent number 9,324,641
- Issue date Apr 26, 2016
- Stats Chippac Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with terminals and method of ma...
- Patent number 9,312,194
- Issue date Apr 12, 2016
- Stats Chippac Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with electrical interface and m...
- Patent number 9,305,873
- Issue date Apr 5, 2016
- Stats Chippac Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with planarity control and meth...
- Patent number 9,293,351
- Issue date Mar 22, 2016
- Stats Chippac Ltd.
- Byung Tai Do
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Integrated circuit packaging system with terminals and method of ma...
- Patent number 9,219,029
- Issue date Dec 22, 2015
- Stats Chippac Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with leadframe and method of ma...
- Patent number 9,190,349
- Issue date Nov 17, 2015
- Stats Chippac Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with trace protection layer and...
- Patent number 9,177,897
- Issue date Nov 3, 2015
- Stats Chippac Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor wafer having through-hole vias on saw streets with ba...
- Patent number 9,177,848
- Issue date Nov 3, 2015
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of stacking die on leadframe electr...
- Patent number 9,177,901
- Issue date Nov 3, 2015
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leadframe system with warp control mechanism and method of manufact...
- Patent number 9,123,712
- Issue date Sep 1, 2015
- Stats Chippac Ltd.
- Byung Tai Do
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit packaging system with routable traces and method...
- Patent number 9,105,620
- Issue date Aug 11, 2015
- Stats Chippac Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor Device and Methods of Making and Using Pre-Molded Bri...
- Publication number 20250149454
- Publication date May 8, 2025
- STATS ChipPAC Pte Ltd.
- Linda Pei Ee Chua
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Fan-Out Package Structur...
- Publication number 20250140730
- Publication date May 1, 2025
- STATS ChipPAC Pte Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Making a Dual-Sided Bridge Die P...
- Publication number 20250132291
- Publication date Apr 24, 2025
- STATS ChipPAC Pte Ltd.
- DanFeng Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Inhibiting Creep of Underfill Ma...
- Publication number 20250118643
- Publication date Apr 10, 2025
- STATS ChipPAC Pte Ltd.
- Yi Jing Eric Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Detecting Semiconductor Wafer Ce...
- Publication number 20250112078
- Publication date Apr 3, 2025
- STATS ChipPAC Pte Ltd.
- Tack Chee Yong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Methods of Making and Using Dummy Vias to...
- Publication number 20250096095
- Publication date Mar 20, 2025
- STATS ChipPAC Pte Ltd.
- Peik Eng Ooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming FOWLP with Pre-Molded Em...
- Publication number 20250087545
- Publication date Mar 13, 2025
- STATS ChipPAC Pte Ltd.
- Kai Chong Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Integrating eWLB with E-bar Stru...
- Publication number 20250038101
- Publication date Jan 30, 2025
- STATS ChipPAC Pte Ltd.
- Ming-Che Hsieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Inverted EWLB Package wi...
- Publication number 20250006608
- Publication date Jan 2, 2025
- STATS ChipPAC Pte Ltd.
- Linda Pei Ee Chua
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Making a Fan-Out Semiconductor P...
- Publication number 20240379479
- Publication date Nov 14, 2024
- STATS ChipPAC Pte Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Stacking Hybrid Substrates with...
- Publication number 20240105630
- Publication date Mar 28, 2024
- STATS ChipPAC Pte Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Stacking Hybrid Substrates
- Publication number 20240096807
- Publication date Mar 21, 2024
- STATS ChipPAC Pte Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Hybrid Substrate with Un...
- Publication number 20240071885
- Publication date Feb 29, 2024
- STATS ChipPAC Pte Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Electromagnetic (EM) Shi...
- Publication number 20170330840
- Publication date Nov 16, 2017
- STATS ChipPAC Pte Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Interconnect Structure a...
- Publication number 20170062390
- Publication date Mar 2, 2017
- STATS ChipPAC Pte Ltd.
- Linda Pei Ee Chua
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Interposer Frame Over Se...
- Publication number 20160111410
- Publication date Apr 21, 2016
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Electromagnetic (EM) Shi...
- Publication number 20150348936
- Publication date Dec 3, 2015
- STATS ChipPAC, Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Embedding Thermally Conductive L...
- Publication number 20150228628
- Publication date Aug 13, 2015
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Stepped Interconnect Lay...
- Publication number 20150145128
- Publication date May 28, 2015
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Using Substrate With Conductive...
- Publication number 20150001707
- Publication date Jan 1, 2015
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Interconnect Structure a...
- Publication number 20140353846
- Publication date Dec 4, 2014
- STATS ChipPAC, Ltd.
- Linda Pei Ee Chua
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED GRID-ARRAY MECHANIS...
- Publication number 20140197548
- Publication date Jul 17, 2014
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSFERABLE TRACE LEAD FRAME
- Publication number 20140167236
- Publication date Jun 19, 2014
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE GRID ARRAY LEAD F...
- Publication number 20140165389
- Publication date Jun 19, 2014
- Byung Tai DO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH GRID-ARRAY MECHANISM AND M...
- Publication number 20140008774
- Publication date Jan 9, 2014
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Cavity Adjacent to Sensi...
- Publication number 20140008769
- Publication date Jan 9, 2014
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Embedding Thermally Conductive L...
- Publication number 20140001627
- Publication date Jan 2, 2014
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Penetrable Film Encapsul...
- Publication number 20130299971
- Publication date Nov 14, 2013
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Through Vias with Reflow...
- Publication number 20130299975
- Publication date Nov 14, 2013
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Interconnect Structure a...
- Publication number 20130292850
- Publication date Nov 7, 2013
- Linda Pei Ee Chua
- H01 - BASIC ELECTRIC ELEMENTS

Linda Pei Ee Chua

Person

Patents Grantslast 30 patents

Semiconductor device and method of forming interposer frame over se...

Semiconductor device and method of forming interposer frame over se...

Semiconductor device and method of forming Fo-WLCSP with recessed i...

Semiconductor device and method of forming electromagnetic (EM) shi...

Integrated circuit packaging system and method of manufacture thereof

Semiconductor device and method of forming interposer frame over se...

Semiconductor device and method of forming stepped interconnect lay...

Integrated circuit packaging system with a grid array with a leadfr...

Semiconductor device and method of forming electromagnetic (EM) shi...

Semiconductor device and method of forming cavity adjacent to sensi...

Integrated circuit packaging system with unplated leadframe and met...

Integrated circuit packaging system with routable trace and method...

Semiconductor device and method of forming interconnect structure a...

Semiconductor device and method of forming base substrate with rece...

Semiconductor device and method of embedding thermally conductive l...

Semiconductor device and method of forming penetrable film encapsul...

Semiconductor device and method of using substrate with conductive...

Semiconductor device and method of forming through vias with reflow...

Integrated circuit packaging system with transferable trace lead frame

Integrated circuit packaging system with external interconnect and...

Integrated circuit packaging system with terminals and method of ma...

Integrated circuit packaging system with electrical interface and m...

Integrated circuit packaging system with planarity control and meth...

Integrated circuit packaging system with terminals and method of ma...

Integrated circuit packaging system with leadframe and method of ma...

Integrated circuit packaging system with trace protection layer and...

Semiconductor wafer having through-hole vias on saw streets with ba...

Semiconductor device and method of stacking die on leadframe electr...

Leadframe system with warp control mechanism and method of manufact...

Integrated circuit packaging system with routable traces and method...

Patents Applicationslast 30 patents

Semiconductor Device and Methods of Making and Using Pre-Molded Bri...

Semiconductor Device and Method of Forming Fan-Out Package Structur...

Semiconductor Device and Method of Making a Dual-Sided Bridge Die P...

Semiconductor Device and Method of Inhibiting Creep of Underfill Ma...

Semiconductor Device and Method of Detecting Semiconductor Wafer Ce...

Semiconductor Device and Methods of Making and Using Dummy Vias to...

Semiconductor Device and Method of Forming FOWLP with Pre-Molded Em...

Semiconductor Device and Method of Integrating eWLB with E-bar Stru...

Semiconductor Device and Method of Forming Inverted EWLB Package wi...

Semiconductor Device and Method of Making a Fan-Out Semiconductor P...

Semiconductor Device and Method of Stacking Hybrid Substrates with...

Semiconductor Device and Method of Stacking Hybrid Substrates

Semiconductor Device and Method of Forming Hybrid Substrate with Un...

Semiconductor Device and Method of Forming Electromagnetic (EM) Shi...

Semiconductor Device and Method of Forming Interconnect Structure a...

Semiconductor Device and Method of Forming Interposer Frame Over Se...

Semiconductor Device and Method of Forming Electromagnetic (EM) Shi...

Semiconductor Device and Method of Embedding Thermally Conductive L...

Semiconductor Device and Method of Forming Stepped Interconnect Lay...

Semiconductor Device and Method of Using Substrate With Conductive...

Semiconductor Device and Method of Forming Interconnect Structure a...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED GRID-ARRAY MECHANIS...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSFERABLE TRACE LEAD FRAME

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE GRID ARRAY LEAD F...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH GRID-ARRAY MECHANISM AND M...

Semiconductor Device and Method of Forming Cavity Adjacent to Sensi...

Semiconductor Device and Method of Embedding Thermally Conductive L...

Semiconductor Device and Method of Forming Penetrable Film Encapsul...

Semiconductor Device and Method of Forming Through Vias with Reflow...

Semiconductor Device and Method of Forming Interconnect Structure a...