Linda Pei Ee Chua

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device and method of forming conductive pillars in re...
- Patent number 8,349,657
- Issue date Jan 8, 2013
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system and method of manufacture thereof
- Patent number 8,334,169
- Issue date Dec 18, 2012
- Stats Chippac Ltd.
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming stepped interconnect lay...
- Patent number 8,283,205
- Issue date Oct 9, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Exposed interconnect for a package on package system
- Patent number 8,270,176
- Issue date Sep 18, 2012
- Stats Chippac Ltd.
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package system with penetrable film adhesive
- Patent number 8,258,015
- Issue date Sep 4, 2012
- Stats Chippac Ltd.
- Seng Guan Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor wafer having through-hole vias on saw streets with ba...
- Patent number 8,247,268
- Issue date Aug 21, 2012
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of embedding thermally conductive l...
- Patent number 8,237,252
- Issue date Aug 7, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mountable integrated circuit package system with mounting interconn...
- Patent number 8,188,586
- Issue date May 29, 2012
- Stats Chippac Ltd.
- Seng Guan Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package-on-package system with anti-mold flash f...
- Patent number 8,183,675
- Issue date May 22, 2012
- Stats Chippac Ltd.
- Seng Guan Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming bond wires and stud bump...
- Patent number 8,168,458
- Issue date May 1, 2012
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of stacking die on leadframe electr...
- Patent number 8,169,058
- Issue date May 1, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming conductive pillars in re...
- Patent number 8,164,184
- Issue date Apr 24, 2012
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with interposer and method of m...
- Patent number 8,143,098
- Issue date Mar 27, 2012
- Stats Chippac Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package system with offset stacking and anti-fla...
- Patent number 8,143,711
- Issue date Mar 27, 2012
- Stats Chippac Ltd.
- Seng Guan Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with through via die having ped...
- Patent number 8,119,447
- Issue date Feb 21, 2012
- Stats Chippac Ltd.
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package system with integral inner lead and paddle
- Patent number 8,110,913
- Issue date Feb 7, 2012
- Stats Chippac Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming stepped interconnect lay...
- Patent number 8,097,490
- Issue date Jan 17, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package having semiconductor die with internal vertic...
- Patent number 8,084,302
- Issue date Dec 27, 2011
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package system with offset stacking
- Patent number 8,084,849
- Issue date Dec 27, 2011
- Stats Chippac Ltd.
- Seng Guan Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming stepped-down RDL and rec...
- Patent number 8,080,882
- Issue date Dec 20, 2011
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system having asymmetric encapsulation...
- Patent number 8,063,477
- Issue date Nov 22, 2011
- Stats Chippac Ltd.
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package system with insulator over circuitry
- Patent number 8,049,314
- Issue date Nov 1, 2011
- Stats Chippac Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of conforming conductive vias betwe...
- Patent number 8,030,136
- Issue date Oct 4, 2011
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package system with slotted die paddle and metho...
- Patent number 8,026,127
- Issue date Sep 27, 2011
- Stats Chippac Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package having through-hole vias on saw streets forme...
- Patent number 8,021,923
- Issue date Sep 20, 2011
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package having through-hole vias on saw streets forme...
- Patent number 8,017,501
- Issue date Sep 13, 2011
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package having through-hole vias on saw streets forme...
- Patent number 8,017,521
- Issue date Sep 13, 2011
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with z-interconnects having tra...
- Patent number 8,003,445
- Issue date Aug 23, 2011
- Stats Chippac Ltd.
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leadless package system having external contacts
- Patent number 7,993,979
- Issue date Aug 9, 2011
- Stats Chippac Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package system with adhesive segment spacer
- Patent number 7,994,624
- Issue date Aug 9, 2011
- Stats Chippac Ltd.
- Linda Pei Ee Chua
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL EMISSION AND METHO...
- Publication number 20120326284
- Publication date Dec 27, 2012
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EXPOSED INTERCONNECT FOR A PACKAGE ON PACKAGE SYSTEM
- Publication number 20120306078
- Publication date Dec 6, 2012
- Reza Argenty Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED INTERCONNECTS AND M...
- Publication number 20120280408
- Publication date Nov 8, 2012
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD...
- Publication number 20120280377
- Publication date Nov 8, 2012
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD...
- Publication number 20120280376
- Publication date Nov 8, 2012
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ELECTRICAL INTERFACE AND M...
- Publication number 20120280407
- Publication date Nov 8, 2012
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Wafer Having Through-Hole Vias on Saw Streets with Ba...
- Publication number 20120273967
- Publication date Nov 1, 2012
- STATS ChipPAC, Ltd.
- Byung Tai DO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Fabricating Semiconductor Die with Through-Hole Via on Sa...
- Publication number 20120244661
- Publication date Sep 27, 2012
- STATS ChipPAC, Ltd.
- Byung Tai DO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILLED VIAS AND METHOD OF...
- Publication number 20120241973
- Publication date Sep 27, 2012
- Linda Pei Ee Chua
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Embedding Thermally Conductive L...
- Publication number 20120241940
- Publication date Sep 27, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TERMINAL LOCKS AND METHOD...
- Publication number 20120205811
- Publication date Aug 16, 2012
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Stacking Die on Leadframe Electr...
- Publication number 20120181673
- Publication date Jul 19, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Bond Wires and Stud Bump...
- Publication number 20120181689
- Publication date Jul 19, 2012
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Conductive Pillars in Re...
- Publication number 20120175770
- Publication date Jul 12, 2012
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Base Substrate with Rece...
- Publication number 20120126429
- Publication date May 24, 2012
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Stepped Interconnect Lay...
- Publication number 20120112355
- Publication date May 10, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Stepped Interconnect Lay...
- Publication number 20120104562
- Publication date May 3, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Penetrable Film Encapsul...
- Publication number 20120104590
- Publication date May 3, 2012
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Package Having Semiconductor Die with Internal Vertic...
- Publication number 20120104599
- Publication date May 3, 2012
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Package Having Semiconductor Die with Internal Vertic...
- Publication number 20120094444
- Publication date Apr 19, 2012
- STATS ChipPAC, Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD ENCAPSULATION AND MET...
- Publication number 20120074547
- Publication date Mar 29, 2012
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ENCAPSULATION AND MET...
- Publication number 20120061855
- Publication date Mar 15, 2012
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DIE PADDLE AND METHOD OF M...
- Publication number 20120032315
- Publication date Feb 9, 2012
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Conforming Conductive Vias Betwe...
- Publication number 20120018900
- Publication date Jan 26, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISLAND TERMINALS AND METHO...
- Publication number 20120018866
- Publication date Jan 26, 2012
- Zigmund Ramirez Camacho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Conforming Conductive Vias Betwe...
- Publication number 20120018899
- Publication date Jan 26, 2012
- STATS ChipPAC, Ltd.
- Reza A. Pagaila
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND M...
- Publication number 20110316163
- Publication date Dec 29, 2011
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STAND-OFF AND METHOD...
- Publication number 20110316133
- Publication date Dec 29, 2011
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEADLESS PACKAGE SYSTEM HAVING EXTERNAL CONTACTS
- Publication number 20110285002
- Publication date Nov 24, 2011
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Interconnect Structure a...
- Publication number 20110278741
- Publication date Nov 17, 2011
- STATS ChipPAC, Ltd.
- Linda Pei Ee Chua
- H01 - BASIC ELECTRIC ELEMENTS

Linda Pei Ee Chua

Person

Patents Grantslast 30 patents

Semiconductor device and method of forming conductive pillars in re...

Integrated circuit packaging system and method of manufacture thereof

Semiconductor device and method of forming stepped interconnect lay...

Exposed interconnect for a package on package system

Integrated circuit package system with penetrable film adhesive

Semiconductor wafer having through-hole vias on saw streets with ba...

Semiconductor device and method of embedding thermally conductive l...

Mountable integrated circuit package system with mounting interconn...

Integrated circuit package-on-package system with anti-mold flash f...

Semiconductor device and method of forming bond wires and stud bump...

Semiconductor device and method of stacking die on leadframe electr...

Semiconductor device and method of forming conductive pillars in re...

Integrated circuit packaging system with interposer and method of m...

Integrated circuit package system with offset stacking and anti-fla...

Integrated circuit packaging system with through via die having ped...

Integrated circuit package system with integral inner lead and paddle

Semiconductor device and method of forming stepped interconnect lay...

Semiconductor package having semiconductor die with internal vertic...

Integrated circuit package system with offset stacking

Semiconductor device and method of forming stepped-down RDL and rec...

Integrated circuit packaging system having asymmetric encapsulation...

Integrated circuit package system with insulator over circuitry

Semiconductor device and method of conforming conductive vias betwe...

Integrated circuit package system with slotted die paddle and metho...

Semiconductor package having through-hole vias on saw streets forme...

Semiconductor package having through-hole vias on saw streets forme...

Semiconductor package having through-hole vias on saw streets forme...

Integrated circuit packaging system with z-interconnects having tra...

Leadless package system having external contacts

Integrated circuit package system with adhesive segment spacer

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL EMISSION AND METHO...

EXPOSED INTERCONNECT FOR A PACKAGE ON PACKAGE SYSTEM

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED INTERCONNECTS AND M...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ELECTRICAL INTERFACE AND M...

Semiconductor Wafer Having Through-Hole Vias on Saw Streets with Ba...

Method of Fabricating Semiconductor Die with Through-Hole Via on Sa...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILLED VIAS AND METHOD OF...

Semiconductor Device and Method of Embedding Thermally Conductive L...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TERMINAL LOCKS AND METHOD...

Semiconductor Device and Method of Stacking Die on Leadframe Electr...

Semiconductor Device and Method of Forming Bond Wires and Stud Bump...

Semiconductor Device and Method of Forming Conductive Pillars in Re...

Semiconductor Device and Method of Forming Base Substrate with Rece...

Semiconductor Device and Method of Forming Stepped Interconnect Lay...

Semiconductor Device and Method of Forming Stepped Interconnect Lay...

Semiconductor Device and Method of Forming Penetrable Film Encapsul...

Semiconductor Package Having Semiconductor Die with Internal Vertic...

Semiconductor Package Having Semiconductor Die with Internal Vertic...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD ENCAPSULATION AND MET...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ENCAPSULATION AND MET...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DIE PADDLE AND METHOD OF M...

Semiconductor Device and Method of Conforming Conductive Vias Betwe...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISLAND TERMINALS AND METHO...

Semiconductor Device and Method of Conforming Conductive Vias Betwe...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND M...

INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STAND-OFF AND METHOD...

LEADLESS PACKAGE SYSTEM HAVING EXTERNAL CONTACTS

Semiconductor Device and Method of Forming Interconnect Structure a...