Ling Cen

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Store performance in strongly ordered microprocessor architecture
- Patent number 8,244,985
- Issue date Aug 14, 2012
- Intel Corporation
- Vladimir Pentkovksi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-hop cache coherency protocol
- Patent number 7,822,929
- Issue date Oct 26, 2010
- Intel Corporation
- Ling Cen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quiescing and de-quiescing point-to-point links
- Patent number 7,761,696
- Issue date Jul 20, 2010
- Intel Corporation
- Binata Bhattacharyya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hot plug interface control method and apparatus
- Patent number 7,673,090
- Issue date Mar 2, 2010
- Intel Corporation
- Shivnandan D. Kaushik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speculatively performing read transactions
- Patent number 7,600,078
- Issue date Oct 6, 2009
- Intel Corporation
- Ling Cen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Store performance in strongly-ordered microprocessor architecture
- Patent number 7,484,045
- Issue date Jan 27, 2009
- Intel Corporation
- Vladimir Pentkovksi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arrangements facilitating ordered transactions
- Patent number 7,471,675
- Issue date Dec 30, 2008
- Intel Corporation
- Ling Cen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for transporting interrupts from secondary PCI...
- Patent number 6,128,691
- Issue date Oct 3, 2000
- Intel Corporation
- Ken C. Haren
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
STORE PERFORMANCE IN STRONGLY ORDERED MICROPROCESSOR ARCHITECTURE
- Publication number 20090144500
- Publication date Jun 4, 2009
- Vladimir Pentkovksi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Two-hop cache coherency protocol
- Publication number 20070022252
- Publication date Jan 25, 2007
- Ling Cen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Messaging protocol
- Publication number 20050262250
- Publication date Nov 24, 2005
- Brannon J. Batson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache coherence protocol
- Publication number 20050240734
- Publication date Oct 27, 2005
- Brannon J. Batson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Store performance
- Publication number 20050223177
- Publication date Oct 6, 2005
- Vladimir Pentkovksi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Arrangements facilitating ordered transactions
- Publication number 20040008677
- Publication date Jan 15, 2004
- Ling Cen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hot plug interface control method and apparatus
- Publication number 20030167367
- Publication date Sep 4, 2003
- Shivnandan D. Kaushik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Node ID discovery
- Publication number 20030131167
- Publication date Jul 10, 2003
- Linda J. Rankin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for enumeration of a multi-node computer system
- Publication number 20030093510
- Publication date May 15, 2003
- Ling Cen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to implement a locked-bus transaction
- Publication number 20020087766
- Publication date Jul 4, 2002
- Akhilesh Kumar
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Store performance in strongly ordered microprocessor architecture

Two-hop cache coherency protocol

Quiescing and de-quiescing point-to-point links

Hot plug interface control method and apparatus

Speculatively performing read transactions

Store performance in strongly-ordered microprocessor architecture

Arrangements facilitating ordered transactions

Apparatus and method for transporting interrupts from secondary PCI...

Patents Applicationslast 30 patents

STORE PERFORMANCE IN STRONGLY ORDERED MICROPROCESSOR ARCHITECTURE

Two-hop cache coherency protocol

Messaging protocol

Cache coherence protocol

Store performance

Arrangements facilitating ordered transactions

Hot plug interface control method and apparatus

Node ID discovery

Method and apparatus for enumeration of a multi-node computer system

Method and apparatus to implement a locked-bus transaction