Lionel D'Luna

Person

Irvine, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Single chip set-top box system
- Patent number 9,668,011
- Issue date May 30, 2017
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Lionel D'Luna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phase controlled high speed interfaces
- Patent number 7,515,504
- Issue date Apr 7, 2009
- Broadcom Corporation
- Lionel J. D'Luna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Custom logic BIST for memory controller
- Patent number 7,496,819
- Issue date Feb 24, 2009
- Broadcom Corporation
- Sathish Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method to align clock signals
- Patent number 7,430,680
- Issue date Sep 30, 2008
- Broadcom Corporation
- Lionel J. D'Luna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase controlled high speed interfaces
- Patent number 7,333,390
- Issue date Feb 19, 2008
- Broadcom Corporation
- Lionel J. D'Luna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Byte slice based DDR timing closure
- Patent number 7,246,341
- Issue date Jul 17, 2007
- Broadcom Corporation
- Lionel D'Luna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Schmoo runtime reduction and dynamic calibration based on a DLL loc...
- Patent number 7,191,279
- Issue date Mar 13, 2007
- Broadcom Corporation
- Sathish Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase controlled high speed interfaces
- Patent number 6,975,557
- Issue date Dec 13, 2005
- Broadcom Corporation
- Lionel J. D'Luna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital resampling integrated circuit for fast image resizing appli...
- Patent number 5,809,182
- Issue date Sep 15, 1998
- Eastman Kodak Company
- Joseph Ward
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Image processor with input buffering to multiple digital signal pro...
- Patent number 5,523,788
- Issue date Jun 4, 1996
- Eastman Kodak Company
- Ram Kannegundla
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Electronic imaging apparatus with dithered color filter array
- Patent number 5,374,956
- Issue date Dec 20, 1994
- Eastman Kodak Company
- Lionel J. D'Luna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Selectively configurable integrated circuit device for performing m...
- Patent number 5,311,459
- Issue date May 10, 1994
- Eastman Kodak Company
- Lionel J. D'Luna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single chip, mode switchable, matrix multiplier and convolver suita...
- Patent number 5,195,050
- Issue date Mar 16, 1993
- Eastman Kodak Company
- Ken W. Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Matrix transpose memory device
- Patent number 5,177,704
- Issue date Jan 5, 1993
- Eastman Kodak Company
- Lionel J. D'Luna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory based line-delay architecture
- Patent number 5,142,494
- Issue date Aug 25, 1992
- Eastman Kodak Company
- Lionel J. D'Luna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal processing circuit for performing a pipelined matrix multipl...
- Patent number 5,109,273
- Issue date Apr 28, 1992
- Eastman Kodak Company
- Kenneth A. Parulski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital correlated double sampling circuit for sampling the output...
- Patent number 5,086,344
- Issue date Feb 4, 1992
- Eastman Kodak Company
- Lionel J. D'Luna
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for compensating for sensitivity variations in...
- Patent number 5,086,343
- Issue date Feb 4, 1992
- Eastman Kodak Company
- William A. Cook
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Distributed digital signal processing system using standard resolut...
- Patent number 5,077,810
- Issue date Dec 31, 1991
- Eastman Kodak Company
- Lionel J. D'Luna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory based line-delay architecture
- Patent number 5,058,065
- Issue date Oct 15, 1991
- Eastman Kodak Company
- Lionel J. D'Luna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for transposing digital data
- Patent number 5,042,007
- Issue date Aug 20, 1991
- Eastman Kodak Company
- Lionel J. D'Luna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Real-time digital processor for producing full resolution color sig...
- Patent number 5,008,739
- Issue date Apr 16, 1991
- Eastman Kodak Company
- Lionel J. D'Luna
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Adjustable clock generator circuit
- Patent number 5,008,563
- Issue date Apr 16, 1991
- Eastman Kodak Company
- Timothy J. Kenney
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable digital circuit for performing a matrix multiplication
- Patent number 5,001,663
- Issue date Mar 19, 1991
- Eastman Kodak Company
- Kenneth A. Parulski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detail processing method and apparatus providing uniform processing...
- Patent number 4,962,419
- Issue date Oct 9, 1990
- Eastman Kodak Company
- Robert H. Hibbard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
Method and System for Receiving Audio, Video and Data Services with...
- Publication number 20080304596
- Publication date Dec 11, 2008
- Loke Tan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Phase Controlled High Speed Interfaces
- Publication number 20080101526
- Publication date May 1, 2008
- BROADCOM CORPORATION
- Lionel J. D'Luna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method to align clock signals
- Publication number 20060156907
- Publication date Jul 20, 2006
- BROADCOM CORPORATION
- Lionel J. D'Luna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Phase controlled high speed interfaces
- Publication number 20060077752
- Publication date Apr 13, 2006
- BROADCOM CORPORATION
- Lionel J. D'Luna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Custom logic BIST for memory controller
- Publication number 20050188255
- Publication date Aug 25, 2005
- Sathish Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
Phase controlled high speed interfaces
- Publication number 20050073902
- Publication date Apr 7, 2005
- Broadcom Corporation
- Lionel J. D'Luna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Byte slice based DDR timing closure
- Publication number 20050050510
- Publication date Mar 3, 2005
- Broadcom Corporation
- Lionel D'Luna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Schmoo runtime reduction and dynamic calibration based on a DLL loc...
- Publication number 20050010714
- Publication date Jan 13, 2005
- Sathish Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
Single chip set-top box system
- Publication number 20020106018
- Publication date Aug 8, 2002
- Lionel D'Luna
- G06 - COMPUTING CALCULATING COUNTING

Lionel D'Luna

Person

Patents Grantslast 30 patents

Single chip set-top box system

Phase controlled high speed interfaces

Custom logic BIST for memory controller

System and method to align clock signals

Phase controlled high speed interfaces

Byte slice based DDR timing closure

Schmoo runtime reduction and dynamic calibration based on a DLL loc...

Phase controlled high speed interfaces

Digital resampling integrated circuit for fast image resizing appli...

Image processor with input buffering to multiple digital signal pro...

Electronic imaging apparatus with dithered color filter array

Selectively configurable integrated circuit device for performing m...

Single chip, mode switchable, matrix multiplier and convolver suita...

Matrix transpose memory device

Memory based line-delay architecture

Signal processing circuit for performing a pipelined matrix multipl...

Digital correlated double sampling circuit for sampling the output...

Method and apparatus for compensating for sensitivity variations in...

Distributed digital signal processing system using standard resolut...

Memory based line-delay architecture

Apparatus for transposing digital data

Real-time digital processor for producing full resolution color sig...

Adjustable clock generator circuit

Programmable digital circuit for performing a matrix multiplication

Detail processing method and apparatus providing uniform processing...

Patents Applicationslast 30 patents

Method and System for Receiving Audio, Video and Data Services with...

Phase Controlled High Speed Interfaces

System and method to align clock signals

Phase controlled high speed interfaces

Custom logic BIST for memory controller

Phase controlled high speed interfaces

Byte slice based DDR timing closure

Schmoo runtime reduction and dynamic calibration based on a DLL loc...

Single chip set-top box system