Liu Liu

Person

Dalian, CN

People

Patents Grantslast 30 patents

Information Patent Grant
3D memory device with top wordline contact located in protected reg...
- Patent number 12,167,592
- Issue date Dec 10, 2024
- Intel Corporation
- Nanda Kumar Chakravarthi
Information Patent Grant
Block-to-block isolation and deep contact using pillars in a memory...
- Patent number 12,120,878
- Issue date Oct 15, 2024
- Intel Corporation
- Deepak Thimmegowda
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated assemblies which include stacked memory decks, and metho...
- Patent number 11,569,258
- Issue date Jan 31, 2023
- Micron Technology, Inc.
- Liu Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated assemblies which include stacked memory decks, and metho...
- Patent number 10,748,921
- Issue date Aug 18, 2020
- Micron Technology, Inc.
- Liu Liu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PARALLEL STAIRCASE 3D NAND
- Publication number 20230200063
- Publication date Jun 22, 2023
- Intel Corporation
- Deepak Thimmegowda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADDITIONAL SILICIDE LAYER ON TOP OF STAIRCASE FOR 3D NAND WL CONTAC...
- Publication number 20230139346
- Publication date May 4, 2023
- Intel Corporation
- Liu LIU
- G11 - INFORMATION STORAGE
Information Patent Application
3D NAND WITH IO CONTACTS IN ISOLATION TRENCH
- Publication number 20230076831
- Publication date Mar 9, 2023
- Intel Corporation
- Praveen Kumar Kalsani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BLOCK-TO-BLOCK ISOLATION AND DEEP CONTACT USING PILLARS IN A MEMORY...
- Publication number 20230036595
- Publication date Feb 2, 2023
- Intel Corporation
- Deepak THIMMEGOWDA
- G11 - INFORMATION STORAGE
Information Patent Application
DUMMY WORDLINE CONTACTS TO IMPROVE ETCH MARGIN OF SEMI-ISOLATED WOR...
- Publication number 20220406352
- Publication date Dec 22, 2022
- Intel Corporation
- Liu LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPLIT BLOCK ARRAY FOR 3D NAND MEMORY
- Publication number 20220399057
- Publication date Dec 15, 2022
- Intel Corporation
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Application
3D MEMORY DEVICE WITH TOP WORDLINE CONTACT LOCATED IN PROTECTED REG...
- Publication number 20220189976
- Publication date Jun 16, 2022
- Intel Corporation
- Nanda Kumar CHAKRAVARTHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Assemblies Which Include Stacked Memory Decks, and Metho...
- Publication number 20200350333
- Publication date Nov 5, 2020
- Micron Technology, Inc.
- Liu Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Assemblies Which Include Stacked Memory Decks, and Metho...
- Publication number 20200135751
- Publication date Apr 30, 2020
- Micron Technology, Inc.
- Liu Liu
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

3D memory device with top wordline contact located in protected reg...

Block-to-block isolation and deep contact using pillars in a memory...

Integrated assemblies which include stacked memory decks, and metho...

Integrated assemblies which include stacked memory decks, and metho...

Patents Applicationslast 30 patents

PARALLEL STAIRCASE 3D NAND

ADDITIONAL SILICIDE LAYER ON TOP OF STAIRCASE FOR 3D NAND WL CONTAC...

3D NAND WITH IO CONTACTS IN ISOLATION TRENCH

BLOCK-TO-BLOCK ISOLATION AND DEEP CONTACT USING PILLARS IN A MEMORY...

DUMMY WORDLINE CONTACTS TO IMPROVE ETCH MARGIN OF SEMI-ISOLATED WOR...

SPLIT BLOCK ARRAY FOR 3D NAND MEMORY

3D MEMORY DEVICE WITH TOP WORDLINE CONTACT LOCATED IN PROTECTED REG...

Integrated Assemblies Which Include Stacked Memory Decks, and Metho...

Integrated Assemblies Which Include Stacked Memory Decks, and Metho...