Liwei Cheng

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Microelectronic assemblies having conductive structures with differ...
- Patent number 12,288,744
- Issue date Apr 29, 2025
- Intel Corporation
- Ji Yong Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual trace thickness for single layer routing
- Patent number 11,769,719
- Issue date Sep 26, 2023
- Intel Corporation
- Jonathan Rosch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vias for package substrates
- Patent number 11,705,389
- Issue date Jul 18, 2023
- Intel Corporation
- Andrew J. Brown
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of tall metal pillars using multiple photoresist layers
- Patent number 11,393,762
- Issue date Jul 19, 2022
- Intel Corporation
- Sri Chaitra J. Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic assemblies having conductive structures with differ...
- Patent number 11,380,609
- Issue date Jul 5, 2022
- Intel Corporation
- Cheng Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plated through hole socketing coupled to a solder ball to engage wi...
- Patent number 10,741,947
- Issue date Aug 11, 2020
- Intel Corporation
- Amruthavalli Pallavi Alur
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SPRAY-COATED PHOTORESIST AND PHOTOIMAGEABLE DIELECTRICS TO ENABLE T...
- Publication number 20240332195
- Publication date Oct 3, 2024
- Intel Corporation
- Naiya SOETAN-DODD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL TRACE THICKNESS FOR SINGLE LAYER ROUTING
- Publication number 20230369192
- Publication date Nov 16, 2023
- Intel Corporation
- Jonathan ROSCH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES HAVING CONDUCTIVE STRUCTURES WITH DIFFER...
- Publication number 20220278038
- Publication date Sep 1, 2022
- Intel Corporation
- Ji Yong Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE FOR AN ELECTRONIC DEVICE
- Publication number 20200411413
- Publication date Dec 31, 2020
- Amruthavalli Pallavi Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIAS FOR PACKAGE SUBSTRATES
- Publication number 20200395282
- Publication date Dec 17, 2020
- Intel Corporation
- Andrew J. BROWN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL TRACE THICKNESS FOR SINGLE LAYER ROUTING
- Publication number 20190393143
- Publication date Dec 26, 2019
- Intel Corporation
- Jonathan ROSCH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES HAVING CONDUCTIVE STRUCTURES WITH DIFFER...
- Publication number 20190355654
- Publication date Nov 21, 2019
- Intel Corporation
- Cheng Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMATION OF TALL METAL PILLARS USING MULTIPLE PHOTORESIST LAYERS
- Publication number 20190326222
- Publication date Oct 24, 2019
- Intel Corporation
- Sri Chaitra J. Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLATED THROUGH HOLE SOCKETING
- Publication number 20190214751
- Publication date Jul 11, 2019
- Amruthavalli Pallavi Alur
- H01 - BASIC ELECTRIC ELEMENTS

Liwei Cheng

Person

Patents Grantslast 30 patents

Microelectronic assemblies having conductive structures with differ...

Dual trace thickness for single layer routing

Vias for package substrates

Formation of tall metal pillars using multiple photoresist layers

Microelectronic assemblies having conductive structures with differ...

Plated through hole socketing coupled to a solder ball to engage wi...

Patents Applicationslast 30 patents

SPRAY-COATED PHOTORESIST AND PHOTOIMAGEABLE DIELECTRICS TO ENABLE T...

DUAL TRACE THICKNESS FOR SINGLE LAYER ROUTING

MICROELECTRONIC ASSEMBLIES HAVING CONDUCTIVE STRUCTURES WITH DIFFER...

SUBSTRATE FOR AN ELECTRONIC DEVICE

VIAS FOR PACKAGE SUBSTRATES

DUAL TRACE THICKNESS FOR SINGLE LAYER ROUTING

MICROELECTRONIC ASSEMBLIES HAVING CONDUCTIVE STRUCTURES WITH DIFFER...

FORMATION OF TALL METAL PILLARS USING MULTIPLE PHOTORESIST LAYERS

PLATED THROUGH HOLE SOCKETING