Lloyd G. Burrell

Person

Poughkepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Bonding structure using two oxide layers with different stress leve...
- Patent number 12,334,461
- Issue date Jun 17, 2025
- GLOBALFOUNDRIES U.S. Inc.
- Jorge A. Lubguban
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming co-planar wafer-scale chip packages
- Patent number 7,867,820
- Issue date Jan 11, 2011
- International Business Machines Corporation
- Lloyd G. Burrell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming co-planar wafer-scale chip packages
- Patent number 7,405,108
- Issue date Jul 29, 2008
- International Business Machines Corporation
- Lloyd G. Burrell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a wire bond pad with Ni/Au metallization
- Patent number 7,294,565
- Issue date Nov 13, 2007
- International Business Machines Corporation
- Lloyd G. Burrell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wirebond crack sensor for low-k die
- Patent number 7,250,311
- Issue date Jul 31, 2007
- International Business Machines Corporation
- Toyohiro Aoki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Copper to aluminum interlayer interconnect using stud and via liner
- Patent number 7,087,997
- Issue date Aug 8, 2006
- International Business Machines Corporation
- Lloyd G. Burrell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Copper to aluminum interlayer interconnect using stud and via liner
- Patent number 7,037,824
- Issue date May 2, 2006
- International Business Machines Corporation
- Lloyd G. Burrell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a composite layer in addition to a barr...
- Patent number 6,960,831
- Issue date Nov 1, 2005
- International Business Machines Corporation
- Lloyd G. Burrell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Support structures for wirebond regions of contact pads over low mo...
- Patent number 6,908,841
- Issue date Jun 21, 2005
- Infineon Technologies AG
- Lloyd G. Burrell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming fusible links
- Patent number 6,559,042
- Issue date May 6, 2003
- International Business Machines Corporation
- Hans-Joachim Barth
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
BONDING STRUCTURE USING TWO OXIDE LAYERS WITH DIFFERENT STRESS LEVE...
- Publication number 20240079360
- Publication date Mar 7, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Jorge A. Lubguban
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for Forming Co-Planar Wafer-Scale Chip Packages
- Publication number 20080280399
- Publication date Nov 13, 2008
- Lloyd G. Burrell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING A WIRE BOND PAD WITH Ni/Au METALLIZATION
- Publication number 20080073790
- Publication date Mar 27, 2008
- International Business Machines Corporation
- Lloyd G. Burrell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WIREBOND CRACK SENSOR FOR LOW-K DIE
- Publication number 20060189007
- Publication date Aug 24, 2006
- International Business Machines Corporation
- Toyohiro Aoki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for forming co-planar wafer-scale chip packages
- Publication number 20060110851
- Publication date May 25, 2006
- International Business Machines Corporation
- Lloyd G. Burrell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Novel integration of wire bond pad with Ni/Au metallization
- Publication number 20050074959
- Publication date Apr 7, 2005
- International Business Machines Corporation
- Lloyd G. Burrell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device having a composite layer in addition to a barr...
- Publication number 20050067708
- Publication date Mar 31, 2005
- International Business Machines Corporation
- Lloyd G. Burrell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Copper to aluminum interlayer interconnect using stud and via liner
- Publication number 20040207092
- Publication date Oct 21, 2004
- Lloyd G. Burrell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Support structures for wirebond regions of contact pads over low mo...
- Publication number 20040058520
- Publication date Mar 25, 2004
- Lloyd G. Burrell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for forming fusible links
- Publication number 20030003703
- Publication date Jan 2, 2003
- International Business Machines Corporation
- Hans-Joachim Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Copper to aluminum interlayer interconnect using stud and via liner
- Publication number 20020127846
- Publication date Sep 12, 2002
- Lloyd G. Burrell
- H01 - BASIC ELECTRIC ELEMENTS

Lloyd G. Burrell

Person

Patents Grantslast 30 patents

Bonding structure using two oxide layers with different stress leve...

Methods for forming co-planar wafer-scale chip packages

Methods for forming co-planar wafer-scale chip packages

Method of fabricating a wire bond pad with Ni/Au metallization

Wirebond crack sensor for low-k die

Copper to aluminum interlayer interconnect using stud and via liner

Copper to aluminum interlayer interconnect using stud and via liner

Semiconductor device having a composite layer in addition to a barr...

Support structures for wirebond regions of contact pads over low mo...

Process for forming fusible links

Patents Applicationslast 30 patents

BONDING STRUCTURE USING TWO OXIDE LAYERS WITH DIFFERENT STRESS LEVE...

Methods for Forming Co-Planar Wafer-Scale Chip Packages

METHOD OF FABRICATING A WIRE BOND PAD WITH Ni/Au METALLIZATION

WIREBOND CRACK SENSOR FOR LOW-K DIE

Methods for forming co-planar wafer-scale chip packages

Novel integration of wire bond pad with Ni/Au metallization

Semiconductor device having a composite layer in addition to a barr...

Copper to aluminum interlayer interconnect using stud and via liner

Support structures for wirebond regions of contact pads over low mo...

Process for forming fusible links

Copper to aluminum interlayer interconnect using stud and via liner