Loren L. McLaury

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Power supply regulation for programmable logic devices
- Patent number 11,316,521
- Issue date Apr 26, 2022
- LATTICE SEMICONDUCTOR CORPORATION
- Loren McLaury
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Deterministic read back and error detection for programmable logic...
- Patent number 10,417,078
- Issue date Sep 17, 2019
- LATTICE SEMICONDUCTOR CORPORATION
- Loren McLaury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Leakage-current abatement circuitry for memory arrays
- Patent number 9,542,993
- Issue date Jan 10, 2017
- Lattice Semiconductor Corporation
- Loren McLaury
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SRAM with two-level voltage regulator
- Patent number 9,286,952
- Issue date Mar 15, 2016
- LATTICE SEMICONDUCTOR CORPORATION
- Loren McLaury
- G11 - INFORMATION STORAGE
Information Patent Grant
Leakage-current abatement circuitry for memory arrays
- Patent number 9,191,022
- Issue date Nov 17, 2015
- LATTICE SEMICONDUCTOR CORPORATION
- Loren McLaury
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage discharge circuit having divided discharge current
- Patent number 8,553,463
- Issue date Oct 8, 2013
- Lattice Semiconductor Corporation
- Robert Gary Pollachek
- G11 - INFORMATION STORAGE
Information Patent Grant
Blocking memory readback in a programmable logic device
- Patent number 8,522,126
- Issue date Aug 27, 2013
- Lattice Semiconductor Corporation
- Zheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Triggered sense amplifier
- Patent number 8,477,549
- Issue date Jul 2, 2013
- Lattice Semiconductor Corporation
- Rohith Sood
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory array with independently erasable sectors
- Patent number 8,059,470
- Issue date Nov 15, 2011
- Lattice Semiconductor Corporation
- Loren McLaury
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic device with built in self test
- Patent number 7,944,765
- Issue date May 17, 2011
- Lattice Semiconductor Corporation
- Wei Han
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory array with independently erasable sectors
- Patent number 7,636,259
- Issue date Dec 22, 2009
- Lallice Semiconductor Corporation
- Loren McLaury
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic device with built in self test
- Patent number 7,630,259
- Issue date Dec 8, 2009
- Lattice Semiconductor Corporation
- Wei Han
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-power output driver buffer circuit
- Patent number 7,605,602
- Issue date Oct 20, 2009
- Lattice Semiconductor Corporation
- Nathan Robert Green
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Negative voltage blocking for embedded memories
- Patent number 7,512,015
- Issue date Mar 31, 2009
- Lattice Semiconductor Corporation
- Loren L. McLaury
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing embedded memory in an integrated circuit
- Patent number 7,484,144
- Issue date Jan 27, 2009
- Lattice Semiconductor Corporation
- Wei Han
- G11 - INFORMATION STORAGE
Information Patent Grant
Single-ended output driver buffer
- Patent number 7,411,414
- Issue date Aug 12, 2008
- Lattice Semiconductor Corporation
- Nathan Robert Green
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory access circuit and method for reading and writing data with...
- Patent number 6,917,536
- Issue date Jul 12, 2005
- Lattice Semiconductor Corporation
- Loren L. McLaury
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM cell with single-ended and differential read/write ports
- Patent number 6,738,306
- Issue date May 18, 2004
- Lattice Semiconductor Corporation
- Loren McLaury
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoded generic routing pool
- Patent number 6,288,937
- Issue date Sep 11, 2001
- Lattice Semiconductor Corporation
- Loren McLaury
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DUAL POWER SUPPLIED MEMORY CELLS AND DETERMINISTIC RESET THEREOF FO...
- Publication number 20240185908
- Publication date Jun 6, 2024
- Lattice Semiconductor Corporation
- Loren L. McLaury
- G11 - INFORMATION STORAGE
Information Patent Application
Clock Insertion Delay Systems and Methods
- Publication number 20240183902
- Publication date Jun 6, 2024
- Lattice Semiconductor Corporation
- Maryam Shahbazi
- G01 - MEASURING TESTING
Information Patent Application
SELECTIVELY POWERED EMBEDDED MEMORY SYSTEMS AND METHODS
- Publication number 20240184459
- Publication date Jun 6, 2024
- Lattice Semiconductor Corporation
- Maryam Shahbazi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER SUPPLY REGULATION FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20210175888
- Publication date Jun 10, 2021
- Lattice Semiconductor Corporation
- Loren McLaury
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DETERMINISTIC READ BACK AND ERROR DETECTION FOR PROGRAMMABLE LOGIC...
- Publication number 20170293518
- Publication date Oct 12, 2017
- Lattice Semiconductor Corporation
- Loren McLaury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Leakage-Current Abatement Circuitry for Memory Arrays
- Publication number 20160099045
- Publication date Apr 7, 2016
- Lattice Semiconductor Corporation
- Loren McLaury
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM WITH TWO-LEVEL VOLTAGE REGULATOR
- Publication number 20150380064
- Publication date Dec 31, 2015
- Lattice Semiconductor Corporation
- Loren McLaury
- G11 - INFORMATION STORAGE
Information Patent Application
Leakage-Current Abatement Circuity for Memory Arrays
- Publication number 20140104934
- Publication date Apr 17, 2014
- Lattice Semiconductor Corporation
- Loren McLaury
- G01 - MEASURING TESTING
Information Patent Application
Testing embedded memory in an integrated circuit
- Publication number 20060059386
- Publication date Mar 16, 2006
- Wei Han
- G11 - INFORMATION STORAGE
Information Patent Application
Multiport SRAM cell
- Publication number 20040052147
- Publication date Mar 18, 2004
- Loren McLaury
- G11 - INFORMATION STORAGE

Loren L. McLaury

Person

Patents Grantslast 30 patents

Power supply regulation for programmable logic devices

Deterministic read back and error detection for programmable logic...

Leakage-current abatement circuitry for memory arrays

SRAM with two-level voltage regulator

Leakage-current abatement circuitry for memory arrays

Voltage discharge circuit having divided discharge current

Blocking memory readback in a programmable logic device

Triggered sense amplifier

Flash memory array with independently erasable sectors

Programmable logic device with built in self test

Flash memory array with independently erasable sectors

Programmable logic device with built in self test

Low-power output driver buffer circuit

Negative voltage blocking for embedded memories

Testing embedded memory in an integrated circuit

Single-ended output driver buffer

Memory access circuit and method for reading and writing data with...

SRAM cell with single-ended and differential read/write ports

Decoded generic routing pool

Patents Applicationslast 30 patents

DUAL POWER SUPPLIED MEMORY CELLS AND DETERMINISTIC RESET THEREOF FO...

Clock Insertion Delay Systems and Methods

SELECTIVELY POWERED EMBEDDED MEMORY SYSTEMS AND METHODS

POWER SUPPLY REGULATION FOR PROGRAMMABLE LOGIC DEVICES

DETERMINISTIC READ BACK AND ERROR DETECTION FOR PROGRAMMABLE LOGIC...

Leakage-Current Abatement Circuitry for Memory Arrays

SRAM WITH TWO-LEVEL VOLTAGE REGULATOR

Leakage-Current Abatement Circuity for Memory Arrays

Testing embedded memory in an integrated circuit

Multiport SRAM cell