Louis Chaochiuan Liu

Person

Hsin-Chu, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Driven metal critical dimension (CD) biasing
- Patent number 8,375,347
- Issue date Feb 12, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Louis Chao-Chiuan Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for performance modeling of integrated circuits
- Patent number 8,365,115
- Issue date Jan 29, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Louis Chao-Chiuan Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for reducing timing libraries for intra-die model in statist...
- Patent number 7,802,209
- Issue date Sep 21, 2010
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Louis Chaochiuan Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SiP (system in package) design systems and methods
- Patent number 7,565,635
- Issue date Jul 21, 2009
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Clinton Chao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design techniques for stacking identical memory dies
- Patent number 7,494,846
- Issue date Feb 24, 2009
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chao-Shun Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for protecting and integrating silicon intellectu...
- Patent number 6,925,614
- Issue date Aug 2, 2005
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Cheng-Yu Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip design with power rails under transistors
- Patent number 6,818,931
- Issue date Nov 16, 2004
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Louis Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Automatic integrated circuit design kit qualification service provi...
- Patent number 6,668,360
- Issue date Dec 23, 2003
- Taiwan Semiconductor Manufacturing Company
- Louis Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip design with power rails under transistors
- Patent number 6,583,045
- Issue date Jun 24, 2003
- Taiwan Semiconductor Manufacturing Company
- Louis Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Utilization of macro power routing area for buffer insertion
- Patent number 6,492,205
- Issue date Dec 10, 2002
- Taiwan Semiconductor Manufacturing Company
- Louis Chao-Chiuan Liu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method for Reducing Timing Libraries for Intra-Die Model in Statist...
- Publication number 20090019409
- Publication date Jan 15, 2009
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Louis Chaochiuan Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIP (SYSTEM IN PACKAGE) DESIGN SYSTEMS AND METHODS
- Publication number 20080250182
- Publication date Oct 9, 2008
- Taiwan Semiconductor Manufacturing Co., LTD
- Clinton Chao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design techniques for stacking identical memory dies
- Publication number 20080220565
- Publication date Sep 11, 2008
- Chao-Shun Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
System and method for protecting and integrating silicon intellectu...
- Publication number 20040199885
- Publication date Oct 7, 2004
- Cheng-Yu Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Chip design with power rails under transistors
- Publication number 20030207523
- Publication date Nov 6, 2003
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
- Louis Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Utilization of MACRO power routing area for buffer insertion
- Publication number 20030049891
- Publication date Mar 13, 2003
- Louis Chao-Chiuan Liu
- H01 - BASIC ELECTRIC ELEMENTS

Louis Chaochiuan Liu

Person

Patents Grantslast 30 patents

Driven metal critical dimension (CD) biasing

System and method for performance modeling of integrated circuits

Method for reducing timing libraries for intra-die model in statist...

SiP (system in package) design systems and methods

Design techniques for stacking identical memory dies

System and method for protecting and integrating silicon intellectu...

Chip design with power rails under transistors

Automatic integrated circuit design kit qualification service provi...

Chip design with power rails under transistors

Utilization of macro power routing area for buffer insertion

Patents Applicationslast 30 patents

Method for Reducing Timing Libraries for Intra-Die Model in Statist...

SIP (SYSTEM IN PACKAGE) DESIGN SYSTEMS AND METHODS

Design techniques for stacking identical memory dies

System and method for protecting and integrating silicon intellectu...

Chip design with power rails under transistors

Utilization of MACRO power routing area for buffer insertion