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Luca Gaetano Amarù
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Jouxtens-Mezery, CH
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Patents Grants
last 30 patents
Information
Patent Grant
Majority logic synthesis
Patent number
10,394,988
Issue date
Aug 27, 2019
Ecole Polytechnique Federale de Lausanne (EPFL)
Pierre-Emmanuel Julien Gaillardon
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Boolean logic optimization in majority-inverter graphs
Patent number
10,380,309
Issue date
Aug 13, 2019
Ecole Polytechnique Federale de Lausanne (EPFL)
Luca Gaetano Amarù
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method for speeding up boolean satisfiability
Patent number
9,685,959
Issue date
Jun 20, 2017
Ecole Polytechnique Federale de Lausanne (EPFL)
Luca Gaetano Amarú
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Controllable polarity FET based arithmetic and differential logic
Patent number
9,130,568
Issue date
Sep 8, 2015
Ecole Polytechnique Federale de Lausanne (EPFL)
Luca Gaetano Amaru
H03 - BASIC ELECTRONIC CIRCUITRY
Patents Applications
last 30 patents
Information
Patent Application
Majority Logic Synthesis
Publication number
20170177750
Publication date
Jun 22, 2017
ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
Pierre-Emmanuel Julien Gaillardon
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
BOOLEAN LOGIC OPTIMIZATION IN MAJORITY-INVERTER GRAPHS
Publication number
20160350469
Publication date
Dec 1, 2016
ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
Luca Gaetano Amarù
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
METHOD FOR SPEEDING UP BOOLEAN SATISFIABILITY
Publication number
20160077154
Publication date
Mar 17, 2016
ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
Luca Gaetano AMARÚ
G01 - MEASURING TESTING
Information
Patent Application
CONTROLLABLE POLARITY FET BASED ARITHMETIC AND DIFFERENTIAL LOGIC
Publication number
20140043060
Publication date
Feb 13, 2014
ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
Luca Gaetano AMARU
H03 - BASIC ELECTRONIC CIRCUITRY