Ludovic Marc Larzul

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Accelerating neuron computations in artificial neural networks by s...
- Patent number 12,205,006
- Issue date Jan 21, 2025
- MIPSOLOGY SAS
- Ludovic Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying structure of artificial neural networks by collocating pa...
- Patent number 11,748,623
- Issue date Sep 5, 2023
- MIPSOLOGY SAS
- Ludovic Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerating neuron computations in artificial neural networks by s...
- Patent number 11,645,510
- Issue date May 9, 2023
- MIPSOLOGY SAS
- Ludovic Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quality monitoring and hidden quantization in artificial neural net...
- Patent number 11,625,583
- Issue date Apr 11, 2023
- MIPSOLOGY SAS
- Frederic Dumoulin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerating neuron computations in artificial neural networks with...
- Patent number 11,494,624
- Issue date Nov 8, 2022
- MIPSOLOGY SAS
- Ludovic Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Realigning streams of neuron outputs in artificial neural network c...
- Patent number 11,126,912
- Issue date Sep 21, 2021
- MIPSOLOGY SAS
- Sebastien Delerse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generic quantization of artificial neural networks
- Patent number 11,068,784
- Issue date Jul 20, 2021
- MIPSOLOGY SAS
- Benoit Chappet de Vangel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerating artificial neural network computations by skipping inp...
- Patent number 10,769,527
- Issue date Sep 8, 2020
- Mipsology SAS
- Sebastien Delerse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient power analysis
- Patent number 10,599,794
- Issue date Mar 24, 2020
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock jitter emulation
- Patent number 10,528,686
- Issue date Jan 7, 2020
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient emulation of circuits
- Patent number 10,127,339
- Issue date Nov 13, 2018
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Isolated debugging in an FPGA based emulation environment
- Patent number 9,959,376
- Issue date May 1, 2018
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient emulation and logic analysis
- Patent number 9,959,375
- Issue date May 1, 2018
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placing and routing debugging logic
- Patent number 9,959,381
- Issue date May 1, 2018
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
X-propagation in emulation using efficient memory
- Patent number 9,910,944
- Issue date Mar 6, 2018
- Synopsys, Inc.
- Alexander Rabinovitch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock jitter emulation
- Patent number 9,898,565
- Issue date Feb 20, 2018
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deterministic identifiers for source code elements
- Patent number 9,858,398
- Issue date Jan 2, 2018
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient waveform generation for emulation
- Patent number 9,852,244
- Issue date Dec 26, 2017
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placing and routing debugging logic
- Patent number 9,817,939
- Issue date Nov 14, 2017
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
X-propagation in emulation using efficient memory
- Patent number 9,773,078
- Issue date Sep 26, 2017
- Synopsys, Inc.
- Alexander Rabinovitch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Isolated debugging in an FPGA based emulation environment
- Patent number 9,684,743
- Issue date Jun 20, 2017
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Isolation of IP units during emulation of a system on a chip
- Patent number 9,684,755
- Issue date Jun 20, 2017
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
X-propagation in emulation
- Patent number 9,659,118
- Issue date May 23, 2017
- Synopsys, Inc.
- Alexander Rabinovitch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient event detection
- Patent number 9,547,040
- Issue date Jan 17, 2017
- Synopsys, Inc.
- Ludovic Marc Larzul
- G01 - MEASURING TESTING
Information Patent Grant
Placing and routing debugging logic
- Patent number 9,547,739
- Issue date Jan 17, 2017
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient waveform generation for emulation
- Patent number 9,286,424
- Issue date Mar 15, 2016
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
OPTIMIZING OPERATIONS IN ARTIFICIAL NEURAL NETWORK
- Publication number 20220222519
- Publication date Jul 14, 2022
- Mipsology SAS
- Ludovic Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODIFYING STRUCTURE OF ARTIFICIAL NEURAL NETWORKS BY COLLOCATING PA...
- Publication number 20210326709
- Publication date Oct 21, 2021
- Mipsology SAS
- Ludovic Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE LOCALLY STORED ARTIFICIAL NEURAL NETWORK COMPUTATIONS
- Publication number 20210117800
- Publication date Apr 22, 2021
- Mipsology SAS
- Stephane Ladevie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATING NEURON COMPUTATIONS IN ARTIFICIAL NEURAL NETWORKS WITH...
- Publication number 20200372328
- Publication date Nov 26, 2020
- Mipsology SAS
- Ludovic Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATING NEURON COMPUTATIONS IN ARTIFICIAL NEURAL NETWORKS BY S...
- Publication number 20200320384
- Publication date Oct 8, 2020
- Mipsology SAS
- Ludovic Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATING NEURON COMPUTATIONS IN ARTIFICIAL NEURAL NETWORKS BY S...
- Publication number 20200311511
- Publication date Oct 1, 2020
- Mipsology SAS
- Ludovic Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUALITY MONITORING AND HIDDEN QUANTIZATION IN ARTIFICIAL NEURAL NET...
- Publication number 20200257966
- Publication date Aug 13, 2020
- Mipsology SAS
- Frederic Dumoulin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERIC QUANTIZATION OF ARTIFICIAL NEURAL NETWORKS
- Publication number 20200242473
- Publication date Jul 30, 2020
- Mipsology SAS
- Benoit Chappet de Vangel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZING ARTIFICIAL NEURAL NETWORK COMPUTATIONS BASED ON AUTOMATI...
- Publication number 20200226458
- Publication date Jul 16, 2020
- Mipsology SAS
- Benoit Chappet de Vangel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REALIGNING STREAMS OF NEURON OUTPUTS IN ARTIFICIAL NEURAL NETWORK C...
- Publication number 20200184322
- Publication date Jun 11, 2020
- Mipsology SAS
- Sebastien Delerse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATING ARTIFICIAL NEURAL NETWORK COMPUTATIONS BY SKIPPING INP...
- Publication number 20200184328
- Publication date Jun 11, 2020
- Mipsology SAS
- Sebastien Delerse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Jitter Emulation
- Publication number 20180129766
- Publication date May 10, 2018
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Placing and Routing Debugging Logic
- Publication number 20180032659
- Publication date Feb 1, 2018
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT EMULATION OF CIRCUITS
- Publication number 20170357743
- Publication date Dec 14, 2017
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
X-Propagation in Emulation Using Efficient Memory
- Publication number 20170337310
- Publication date Nov 23, 2017
- Synopsys, Inc.
- ALEXANDER RABINOVITCH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Isolated Debugging in an FPGA Based Emulation Environment
- Publication number 20170193146
- Publication date Jul 6, 2017
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Jitter Emulation
- Publication number 20170147725
- Publication date May 25, 2017
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Deterministic Identifiers for Source Code Elements
- Publication number 20170124305
- Publication date May 4, 2017
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SAVING AND RESTORING AN EMULATION ENVIRONMENT
- Publication number 20170083652
- Publication date Mar 23, 2017
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Placing and Routing Debugging Logic
- Publication number 20170083655
- Publication date Mar 23, 2017
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ISOLATED DEBUGGING IN AN FPGA BASED EMULATION ENVIRONMENT
- Publication number 20160371407
- Publication date Dec 22, 2016
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ISOLATION OF IP UNITS DURING EMULATION OF A SYSTEM ON A CHIP
- Publication number 20160342725
- Publication date Nov 24, 2016
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLACING AND ROUTING DEBUGGING LOGIC
- Publication number 20160342721
- Publication date Nov 24, 2016
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT EVENT DETECTION
- Publication number 20160327609
- Publication date Nov 10, 2016
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G01 - MEASURING TESTING
Information Patent Application
Efficient Waveform Generation for Emulation
- Publication number 20160328499
- Publication date Nov 10, 2016
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FPGA Trace Memory
- Publication number 20160314232
- Publication date Oct 27, 2016
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
X-PROPAGATION IN EMULATION
- Publication number 20160217235
- Publication date Jul 28, 2016
- Synopsys, Inc.
- ALEXANDER RABINOVITCH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
X-PROPAGATION IN EMULATION USING EFFICIENT MEMORY
- Publication number 20160217236
- Publication date Jul 28, 2016
- Synopsys, Inc.
- ALEXANDER RABINOVITCH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT POWER ANALYSIS
- Publication number 20160098504
- Publication date Apr 7, 2016
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT EMULATION AND LOGIC ANALYSIS
- Publication number 20160098505
- Publication date Apr 7, 2016
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G06 - COMPUTING CALCULATING COUNTING

Ludovic Marc Larzul

Person

Patents Grantslast 30 patents

Accelerating neuron computations in artificial neural networks by s...

Modifying structure of artificial neural networks by collocating pa...

Accelerating neuron computations in artificial neural networks by s...

Quality monitoring and hidden quantization in artificial neural net...

Accelerating neuron computations in artificial neural networks with...

Realigning streams of neuron outputs in artificial neural network c...

Generic quantization of artificial neural networks

Accelerating artificial neural network computations by skipping inp...

Efficient power analysis

Clock jitter emulation

Efficient emulation of circuits

Isolated debugging in an FPGA based emulation environment

Efficient emulation and logic analysis

Placing and routing debugging logic

X-propagation in emulation using efficient memory

Clock jitter emulation

Deterministic identifiers for source code elements

Efficient waveform generation for emulation

Placing and routing debugging logic

X-propagation in emulation using efficient memory

Isolated debugging in an FPGA based emulation environment

Isolation of IP units during emulation of a system on a chip

X-propagation in emulation

Efficient event detection

Placing and routing debugging logic

Efficient waveform generation for emulation

Patents Applicationslast 30 patents

OPTIMIZING OPERATIONS IN ARTIFICIAL NEURAL NETWORK

MODIFYING STRUCTURE OF ARTIFICIAL NEURAL NETWORKS BY COLLOCATING PA...

MULTIPLE LOCALLY STORED ARTIFICIAL NEURAL NETWORK COMPUTATIONS

ACCELERATING NEURON COMPUTATIONS IN ARTIFICIAL NEURAL NETWORKS WITH...

ACCELERATING NEURON COMPUTATIONS IN ARTIFICIAL NEURAL NETWORKS BY S...

ACCELERATING NEURON COMPUTATIONS IN ARTIFICIAL NEURAL NETWORKS BY S...

QUALITY MONITORING AND HIDDEN QUANTIZATION IN ARTIFICIAL NEURAL NET...

GENERIC QUANTIZATION OF ARTIFICIAL NEURAL NETWORKS

OPTIMIZING ARTIFICIAL NEURAL NETWORK COMPUTATIONS BASED ON AUTOMATI...

REALIGNING STREAMS OF NEURON OUTPUTS IN ARTIFICIAL NEURAL NETWORK C...

ACCELERATING ARTIFICIAL NEURAL NETWORK COMPUTATIONS BY SKIPPING INP...

Clock Jitter Emulation

Placing and Routing Debugging Logic

EFFICIENT EMULATION OF CIRCUITS

X-Propagation in Emulation Using Efficient Memory

Isolated Debugging in an FPGA Based Emulation Environment

Clock Jitter Emulation

Deterministic Identifiers for Source Code Elements

SAVING AND RESTORING AN EMULATION ENVIRONMENT

Placing and Routing Debugging Logic

ISOLATED DEBUGGING IN AN FPGA BASED EMULATION ENVIRONMENT

ISOLATION OF IP UNITS DURING EMULATION OF A SYSTEM ON A CHIP

PLACING AND ROUTING DEBUGGING LOGIC

EFFICIENT EVENT DETECTION

Efficient Waveform Generation for Emulation

FPGA Trace Memory

X-PROPAGATION IN EMULATION

X-PROPAGATION IN EMULATION USING EFFICIENT MEMORY

EFFICIENT POWER ANALYSIS

EFFICIENT EMULATION AND LOGIC ANALYSIS