Lukas DAELLENBACH

Person

Boeblingen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor circuit design and unit pin placement
- Patent number 11,354,478
- Issue date Jun 7, 2022
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor circuit design and unit pin placement
- Patent number 10,997,350
- Issue date May 4, 2021
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sink-based wire tagging in multi-sink integrated circuit net
- Patent number 10,936,773
- Issue date Mar 2, 2021
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing routing of a signal path in a semiconductor device
- Patent number 10,353,841
- Issue date Jul 16, 2019
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing based net constraints tagging with zero wire load validation
- Patent number 10,031,996
- Issue date Jul 24, 2018
- International Business Machines Corporation
- Florian Braun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for calculating an effect on timing of moving a pin from an...
- Patent number 9,727,687
- Issue date Aug 8, 2017
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for calculating an effect on timing of moving a pin from an...
- Patent number 9,418,198
- Issue date Aug 16, 2016
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimized buffer placement based on timing and capacitance assertions
- Patent number 8,930,870
- Issue date Jan 6, 2015
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimized buffer placement based on timing and capacitance assertions
- Patent number 8,566,774
- Issue date Oct 22, 2013
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Early noise detection and noise aware routing in circuit design
- Patent number 8,423,940
- Issue date Apr 16, 2013
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for routing of integrated circuit design
- Patent number 7,966,597
- Issue date Jun 21, 2011
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTI-LAYER INTEGRATED CIRCUIT ROUTING TOOL
- Publication number 20240037311
- Publication date Feb 1, 2024
- International Business Machines Corporation
- Ralf Richter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR CIRCUIT DESIGN AND UNIT PIN PLACEMENT
- Publication number 20220004691
- Publication date Jan 6, 2022
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINK-BASED WIRE TAGGING IN MULTI-SINK INTEGRATED CIRCUIT NET
- Publication number 20210064711
- Publication date Mar 4, 2021
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RE-ROUTING TIME CRITICAL MULTI-SINK NETS IN CHIP DESIGN
- Publication number 20200050730
- Publication date Feb 13, 2020
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING BASED NET CONSTRAINTS TAGGING WITH ZERO WIRE LOAD VALIDATION
- Publication number 20180165405
- Publication date Jun 14, 2018
- International Business Machines Corporation
- Florian BRAUN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZING ROUTING OF A SIGNAL PATH IN A SEMICONDUCTOR DEVICE
- Publication number 20180165239
- Publication date Jun 14, 2018
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR CALCULATING AN EFFECT ON TIMING OF MOVING A PIN FROM AN...
- Publication number 20160232273
- Publication date Aug 11, 2016
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR CALCULATING AN EFFECT ON TIMING OF MOVING A PIN FROM AN...
- Publication number 20160232276
- Publication date Aug 11, 2016
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZED BUFFER PLACEMENT BASED ON TIMING AND CAPACITANCE ASSERTIONS
- Publication number 20140019665
- Publication date Jan 16, 2014
- International Business Machines Corporation
- Lukas DAELLENBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EARLY NOISE DETECTION AND NOISE AWARE ROUTING IN CIRCUIT DESIGN
- Publication number 20130047130
- Publication date Feb 21, 2013
- IBM Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZED BUFFER PLACEMENT BASED ON TIMING AND CAPACITANCE ASSERTIONS
- Publication number 20120151193
- Publication date Jun 14, 2012
- International Business Machines Corporation
- Lukas DAELLENBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Routing of Integrated Circuit Design
- Publication number 20080301618
- Publication date Dec 4, 2008
- International Business Machines Corporation
- Lukas Daellenbach
- G06 - COMPUTING CALCULATING COUNTING

Lukas DAELLENBACH

Person

Patents Grantslast 30 patents

Semiconductor circuit design and unit pin placement

Semiconductor circuit design and unit pin placement

Sink-based wire tagging in multi-sink integrated circuit net

Optimizing routing of a signal path in a semiconductor device

Timing based net constraints tagging with zero wire load validation

Method for calculating an effect on timing of moving a pin from an...

Method for calculating an effect on timing of moving a pin from an...

Optimized buffer placement based on timing and capacitance assertions

Optimized buffer placement based on timing and capacitance assertions

Early noise detection and noise aware routing in circuit design

Method and system for routing of integrated circuit design

Patents Applicationslast 30 patents

MULTI-LAYER INTEGRATED CIRCUIT ROUTING TOOL

SEMICONDUCTOR CIRCUIT DESIGN AND UNIT PIN PLACEMENT

SINK-BASED WIRE TAGGING IN MULTI-SINK INTEGRATED CIRCUIT NET

RE-ROUTING TIME CRITICAL MULTI-SINK NETS IN CHIP DESIGN

TIMING BASED NET CONSTRAINTS TAGGING WITH ZERO WIRE LOAD VALIDATION

OPTIMIZING ROUTING OF A SIGNAL PATH IN A SEMICONDUCTOR DEVICE

METHOD FOR CALCULATING AN EFFECT ON TIMING OF MOVING A PIN FROM AN...

METHOD FOR CALCULATING AN EFFECT ON TIMING OF MOVING A PIN FROM AN...

OPTIMIZED BUFFER PLACEMENT BASED ON TIMING AND CAPACITANCE ASSERTIONS

EARLY NOISE DETECTION AND NOISE AWARE ROUTING IN CIRCUIT DESIGN

OPTIMIZED BUFFER PLACEMENT BASED ON TIMING AND CAPACITANCE ASSERTIONS

Method and System for Routing of Integrated Circuit Design