Lun Zhao

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Capacitor top plate over source/drain to form a 1T memory device
- Patent number 8,716,081
- Issue date May 6, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Lee Wee Teo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid orientation substrate with stress layer
- Patent number 8,274,115
- Issue date Sep 25, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Lee Wee Teo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming shallow trench isolation structures for integrate...
- Patent number 8,178,417
- Issue date May 15, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Shailendra Mishra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nested and isolated transistors with reduced impedance difference
- Patent number 8,143,651
- Issue date Mar 27, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Johnny Widodo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacture of an integrated circuit system with self-ali...
- Patent number 8,053,327
- Issue date Nov 8, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Shailendra Mishra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell structure and method for fabrication thereof
- Patent number 7,999,300
- Issue date Aug 16, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Zhao Lun
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Integrated circuit having a plurality of MOSFET devices
- Patent number 7,932,178
- Issue date Apr 26, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Lee Wee Teo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of forming integrated circuit devices having ion-cured elec...
- Patent number 7,838,390
- Issue date Nov 23, 2010
- Samsung Electronics Co., Ltd.
- Jun-jung Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system employing selective epitaxial growth tech...
- Patent number 7,795,680
- Issue date Sep 14, 2010
- Chartered Semiconductor Manufacturing Ltd.
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nested and isolated transistors with reduced impedance difference
- Patent number 7,767,577
- Issue date Aug 3, 2010
- Chartered Semiconductor Manufacturing, Ltd.
- Johnny Widodo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and fabrication method
- Patent number 7,326,609
- Issue date Feb 5, 2008
- Chartered Semiconductor Manufacturing, Ltd.
- Purakh Raj Verma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow low energy ion implantation into pad oxide for improving th...
- Patent number 7,259,072
- Issue date Aug 21, 2007
- Chartered Semiconductor Manufacturing Ltd.
- Yisuo Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a partially depleted silicon on insulator (PDSOI)...
- Patent number 6,998,682
- Issue date Feb 14, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Yeen Tat Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a partially depleted silicon on insulator (PDSOI)...
- Patent number 6,905,919
- Issue date Jun 14, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Yeen Tat Chan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE
- Publication number 20100301424
- Publication date Dec 2, 2010
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Johnny WIDODO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL STRUCTURE AND METHOD FOR FABRICATION THEREOF
- Publication number 20100187587
- Publication date Jul 29, 2010
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Zhao LUN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM EMPLOYING SINGLE MASK LAYER TECHNIQUE FOR...
- Publication number 20100009527
- Publication date Jan 14, 2010
- Chartered Semiconductor Manufacturing LTD.
- Yong Meng Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURES FOR INTEGRATE...
- Publication number 20090261448
- Publication date Oct 22, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Shailendra MISHRA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID ORIENTATION SUBSTRATE WITH STRESS LAYER
- Publication number 20090236663
- Publication date Sep 24, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Lee Wee Teo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE
- Publication number 20090206408
- Publication date Aug 20, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Johnny WIDODO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM EMPLOYING SELECTIVE EPITAXIAL GROWTH TECH...
- Publication number 20090146262
- Publication date Jun 11, 2009
- Chartered Semiconductor Manufacturing LTD.
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of Forming Integrated Circuit Devices Having Ion-Cured Elec...
- Publication number 20090098706
- Publication date Apr 16, 2009
- SAMSUNG ELECTRONICS CO., LTD.
- Jun-jung Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAPACITOR TOP PLATE OVER SOURCE/DRAIN TO FORM A 1T MEMORY DEVICE
- Publication number 20080224228
- Publication date Sep 18, 2008
- Lee Wee Teo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT HAVING A PLURALITY OF MOSFET DEVICES
- Publication number 20080157223
- Publication date Jul 3, 2008
- Chartered Semiconductor Manufacturing LTD.
- Lee Wee Teo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT SYSTEM WITH ISOLATION
- Publication number 20080150074
- Publication date Jun 26, 2008
- Chartered Semiconductor Manufacturing LTD.
- Shailendra Mishra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH DOPED TRANSISTOR
- Publication number 20080087958
- Publication date Apr 17, 2008
- Chartered Semiconductor Manufacturing LTD.
- Purakh Raj Verma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND FABRICATION METHOD
- Publication number 20060252188
- Publication date Nov 9, 2006
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Purakh Raj Verma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM FOR DIFFERENT BOND PADS IN AN INTEGRATED CIRCUIT PACKAGE
- Publication number 20060197223
- Publication date Sep 7, 2006
- ST ASSEMBLY TEST SERVICES LTD.
- Lun Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Shallow low energy ion implantation into pad oxide for improving th...
- Publication number 20050239256
- Publication date Oct 27, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Yisuo Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a partially depleted silicon on insulator (PDSOI)...
- Publication number 20050208712
- Publication date Sep 22, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Yeen Tat Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a partially depleted silicon on insulator (PDSOI)...
- Publication number 20050023608
- Publication date Feb 3, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Yeen Tat Chan
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Capacitor top plate over source/drain to form a 1T memory device

Hybrid orientation substrate with stress layer

Method of forming shallow trench isolation structures for integrate...

Nested and isolated transistors with reduced impedance difference

Method of manufacture of an integrated circuit system with self-ali...

Memory cell structure and method for fabrication thereof

Integrated circuit having a plurality of MOSFET devices

Methods of forming integrated circuit devices having ion-cured elec...

Integrated circuit system employing selective epitaxial growth tech...

Nested and isolated transistors with reduced impedance difference

Semiconductor device and fabrication method

Shallow low energy ion implantation into pad oxide for improving th...

Method of forming a partially depleted silicon on insulator (PDSOI)...

Method of forming a partially depleted silicon on insulator (PDSOI)...

Patents Applicationslast 30 patents

NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE

MEMORY CELL STRUCTURE AND METHOD FOR FABRICATION THEREOF

INTEGRATED CIRCUIT SYSTEM EMPLOYING SINGLE MASK LAYER TECHNIQUE FOR...

METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURES FOR INTEGRATE...

HYBRID ORIENTATION SUBSTRATE WITH STRESS LAYER

NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE

INTEGRATED CIRCUIT SYSTEM EMPLOYING SELECTIVE EPITAXIAL GROWTH TECH...

Methods of Forming Integrated Circuit Devices Having Ion-Cured Elec...

CAPACITOR TOP PLATE OVER SOURCE/DRAIN TO FORM A 1T MEMORY DEVICE

INTEGRATED CIRCUIT HAVING A PLURALITY OF MOSFET DEVICES

INTEGRATED CIRCUIT SYSTEM WITH ISOLATION

SEMICONDUCTOR DEVICE WITH DOPED TRANSISTOR

SEMICONDUCTOR DEVICE AND FABRICATION METHOD

SYSTEM FOR DIFFERENT BOND PADS IN AN INTEGRATED CIRCUIT PACKAGE

Shallow low energy ion implantation into pad oxide for improving th...

Method of forming a partially depleted silicon on insulator (PDSOI)...

Method of forming a partially depleted silicon on insulator (PDSOI)...