M. Clair Webb

Person

North Logan, UT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Silicon die with integrated high voltage devices
- Patent number 10,700,039
- Issue date Jun 30, 2020
- Intel Corporation
- Donald W. Nelson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Monolithic three-dimensional (3D) ICs with local inter-level interc...
- Patent number 10,297,592
- Issue date May 21, 2019
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for direct integration of memory die to logic die without us...
- Patent number 10,068,874
- Issue date Sep 4, 2018
- Intel Corporation
- Donald W. Nelson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming under device interconnect structures
- Patent number 9,721,898
- Issue date Aug 1, 2017
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Monolithic three-dimensional (3D) ICs with local inter-level interc...
- Patent number 9,685,436
- Issue date Jun 20, 2017
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming under device interconnect structures
- Patent number 9,490,201
- Issue date Nov 8, 2016
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-die processor
- Patent number 8,860,199
- Issue date Oct 14, 2014
- Intel Corporation
- Bryan P. Black
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
6F2 DRAM cell
- Patent number 8,519,462
- Issue date Aug 27, 2013
- Intel Corporation
- Yih Wang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MONOLITHIC THREE-DIMENSIONAL (3D) ICs WITH LOCAL INTER-LEVEL INTERC...
- Publication number 20170287905
- Publication date Oct 5, 2017
- Intel Corporation
- Patrick MORROW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED MEMORY IN INTERCONNECT STACK ON SILICON DIE
- Publication number 20170077389
- Publication date Mar 16, 2017
- Intel Corporation
- Donald W. NELSON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR DIRECT INTEGRATION OF MEMORY DIE TO LOGIC DIE WITHOUT US...
- Publication number 20170069598
- Publication date Mar 9, 2017
- Intel Corporation
- Donald W. NELSON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICON DIE WITH INTEGRATED HIGH VOLTAGE DEVICES
- Publication number 20170069597
- Publication date Mar 9, 2017
- Intel Corporation
- Donald W. NELSON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING UNDER DEVICE INTERCONNECT STRUCTURES
- Publication number 20170025355
- Publication date Jan 26, 2017
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MONOLITHIC THREE-DIMENSIONAL (3D) ICs WITH LOCAL INTER-LEVEL INTERC...
- Publication number 20160197069
- Publication date Jul 7, 2016
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
6F2 DRAM Cell
- Publication number 20120326218
- Publication date Dec 27, 2012
- Yih Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-Die Processor
- Publication number 20090138688
- Publication date May 28, 2009
- Bryan P. Black
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-die processor
- Publication number 20050127490
- Publication date Jun 16, 2005
- Bryan P. Black
- G06 - COMPUTING CALCULATING COUNTING

M. Clair Webb

Person

Patents Grantslast 30 patents

Silicon die with integrated high voltage devices

Monolithic three-dimensional (3D) ICs with local inter-level interc...

Method for direct integration of memory die to logic die without us...

Methods of forming under device interconnect structures

Monolithic three-dimensional (3D) ICs with local inter-level interc...

Methods of forming under device interconnect structures

Multi-die processor

6F2 DRAM cell

Patents Applicationslast 30 patents

MONOLITHIC THREE-DIMENSIONAL (3D) ICs WITH LOCAL INTER-LEVEL INTERC...

EMBEDDED MEMORY IN INTERCONNECT STACK ON SILICON DIE

METHOD FOR DIRECT INTEGRATION OF MEMORY DIE TO LOGIC DIE WITHOUT US...

SILICON DIE WITH INTEGRATED HIGH VOLTAGE DEVICES

METHODS OF FORMING UNDER DEVICE INTERCONNECT STRUCTURES

MONOLITHIC THREE-DIMENSIONAL (3D) ICs WITH LOCAL INTER-LEVEL INTERC...

6F2 DRAM Cell

Multi-Die Processor

Multi-die processor