Maad Al-Dabagh

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of finding critical nets in an integrated circuit design
- Patent number 7,107,558
- Issue date Sep 12, 2006
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated design system and method for reducing and avoiding cross...
- Patent number 6,907,586
- Issue date Jun 14, 2005
- LSI Logic Corporation
- Maad A. Al-Dabagh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design system and method for reducing and avoidi...
- Patent number 6,907,590
- Issue date Jun 14, 2005
- LSI Logic Corporation
- Maad A. Al-Dabagh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design flow with capacitive margin
- Patent number 6,810,505
- Issue date Oct 26, 2004
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoupling capacitance estimation and insertion flow for ASIC designs
- Patent number 6,807,656
- Issue date Oct 19, 2004
- LSI Logic Corporation
- Lihui Cao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Donut power mesh scheme for flip chip package
- Patent number 6,781,228
- Issue date Aug 24, 2004
- LSI Logic Corporation
- Hiroshi Ishikawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Termination ring for integrated circuit
- Patent number 6,747,349
- Issue date Jun 8, 2004
- LSI Logic Corporation
- Maad Al-Dabagh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interleaved termination ring
- Patent number 6,744,081
- Issue date Jun 1, 2004
- LSI Logic Corporation
- Radoslav Ratchkov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated design system and method for reducing and avoiding cross...
- Patent number 6,594,805
- Issue date Jul 15, 2003
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method of finding critical nets in an integrated circuit design
- Publication number 20050022145
- Publication date Jan 27, 2005
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DECOUPLING CAPACITANCE ESTIMATION AND INSERTION FLOW FOR ASIC DESIGNS
- Publication number 20040199882
- Publication date Oct 7, 2004
- Lihui Cao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Donut power mesh scheme for flip chip package
- Publication number 20040135263
- Publication date Jul 15, 2004
- Hiroshi Ishikawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TERMINATION RING FOR INTEGRATED CIRCUIT
- Publication number 20040124521
- Publication date Jul 1, 2004
- Maad Al-Dabagh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERLEAVED TERMINATION RING
- Publication number 20040085099
- Publication date May 6, 2004
- Radoslav Ratchkov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit design flow with capacitive margin
- Publication number 20040010761
- Publication date Jan 15, 2004
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING

Maad Al-Dabagh

Person

Patents Grantslast 30 patents

Method of finding critical nets in an integrated circuit design

Integrated design system and method for reducing and avoiding cross...

Integrated circuit design system and method for reducing and avoidi...

Integrated circuit design flow with capacitive margin

Decoupling capacitance estimation and insertion flow for ASIC designs

Donut power mesh scheme for flip chip package

Termination ring for integrated circuit

Interleaved termination ring

Integrated design system and method for reducing and avoiding cross...

Patents Applicationslast 30 patents

Method of finding critical nets in an integrated circuit design

DECOUPLING CAPACITANCE ESTIMATION AND INSERTION FLOW FOR ASIC DESIGNS

Donut power mesh scheme for flip chip package

TERMINATION RING FOR INTEGRATED CIRCUIT

INTERLEAVED TERMINATION RING

Integrated circuit design flow with capacitive margin