Mack W. Riley

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Circuit design for balanced logic stress
- Patent number 9,383,767
- Issue date Jul 5, 2016
- International Business Machines Corporation
- Nathaniel R. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Evaluation of multiple input signature register results
- Patent number 9,336,105
- Issue date May 10, 2016
- International Business Machines Corporation
- Mack Wayne Riley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design for balanced logic stress
- Patent number 9,250,645
- Issue date Feb 2, 2016
- International Business Machines Corporation
- Nathaniel R. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip detection of types of operations tested by an LBIST
- Patent number 9,128,150
- Issue date Sep 8, 2015
- International Business Machines Corporation
- Michael W. Harper
- G11 - INFORMATION STORAGE
Information Patent Grant
Isolating failing latches using a logic built-in self-test
- Patent number 9,057,766
- Issue date Jun 16, 2015
- International Business Machines Corporation
- Ra'ed M. Al-omari
- G01 - MEASURING TESTING
Information Patent Grant
Determining chip burn-in workload using emulated application condition
- Patent number 8,943,458
- Issue date Jan 27, 2015
- International Business Machines Corporation
- Nathaniel R. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip detection of types of operations tested by an LBIST
- Patent number 8,943,377
- Issue date Jan 27, 2015
- International Business Machines Corporation
- Michael W. Harper
- G11 - INFORMATION STORAGE
Information Patent Grant
Information collection and storage for single core chips to 'N core...
- Patent number 8,639,855
- Issue date Jan 28, 2014
- International Business Machines Corporation
- Michael W. Harper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling asynchronous clock domains to perform synchronous opera...
- Patent number 8,144,689
- Issue date Mar 27, 2012
- International Business Machines Corporation
- Nathan P. Chelstrom
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital thermal sensor test implementation without using main core...
- Patent number 8,027,798
- Issue date Sep 27, 2011
- International Business Machines Corporation
- Charles R. Johns
- G01 - MEASURING TESTING
Information Patent Grant
Testing functional boundary logic at asynchronous clock boundaries...
- Patent number 7,908,536
- Issue date Mar 15, 2011
- International Business Machines Corporation
- Nathan P. Chelstrom
- G01 - MEASURING TESTING
Information Patent Grant
Secure power-on reset engine
- Patent number 7,895,426
- Issue date Feb 22, 2011
- International Business Machines Corporation
- Ingemar Holm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit to reduce transient current swings during mode transitions...
- Patent number 7,831,006
- Issue date Nov 9, 2010
- International Business Machines Corporation
- David William Boerstler
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Circuit to reduce power supply fluctuations in high frequency/high...
- Patent number 7,809,974
- Issue date Oct 5, 2010
- International Business Machines Corporation
- David William Boerstler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling asynchronous clock domains to perform synchronous opera...
- Patent number 7,792,154
- Issue date Sep 7, 2010
- International Business Machines Corporation
- Nathan P. Chelstrom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
eFuse programming data alignment verification
- Patent number 7,721,168
- Issue date May 18, 2010
- International Business Machines Corporation
- Mack W. Riley
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed on-chip serial link apparatus
- Patent number 7,711,875
- Issue date May 4, 2010
- International Business Machines Corporation
- Tilman Gloekler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic frequency scaling sequence for multi-gigahertz microprocessors
- Patent number 7,702,944
- Issue date Apr 20, 2010
- International Business Machines Corporation
- Nathan Chelstrom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a single bank of efuses to successively store testing data fr...
- Patent number 7,698,608
- Issue date Apr 13, 2010
- International Business Machines Corporation
- Mack Wayne Riley
- G11 - INFORMATION STORAGE
Information Patent Grant
Using eFuses to store PLL configuration data
- Patent number 7,688,930
- Issue date Mar 30, 2010
- International Business Machines Corporation
- Irene Beattie
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method to gate off PLLS in a deep power saving state without separa...
- Patent number 7,656,237
- Issue date Feb 2, 2010
- International Business Machines Corporation
- Mack Wayne Riley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock control hierarchy for integrated microprocessors and systems-...
- Patent number 7,627,771
- Issue date Dec 1, 2009
- International Business Machines Corporation
- Nathan P. Chelstrom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for detecting frequency lock in a system inclu...
- Patent number 7,620,126
- Issue date Nov 17, 2009
- International Business Machines Corporation
- David William Boerstler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Modifying a test pattern to control power supply noise
- Patent number 7,610,531
- Issue date Oct 27, 2009
- International Business Machines Corporation
- Sang H. Dhong
- G01 - MEASURING TESTING
Information Patent Grant
Information handling system capable of detecting frequency lock of...
- Patent number 7,590,194
- Issue date Sep 15, 2009
- International Business Machines Corporation
- David William Boerstler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for using eFuses to store PLL configuration data
- Patent number 7,562,272
- Issue date Jul 14, 2009
- International Business Machines Corporation
- Irene Beattie
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for advanced logic built-in self test with select...
- Patent number 7,546,504
- Issue date Jun 9, 2009
- International Business Machines Corporation
- Mack Wayne Riley
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic frequency scaling sequence for multi-gigahertz microprocessors
- Patent number 7,516,350
- Issue date Apr 7, 2009
- International Business Machines Corporation
- Nathan Chelstrom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for reducing test time for loading and executing...
- Patent number 7,512,925
- Issue date Mar 31, 2009
- International Business Machines Corporation
- Parag Birmiwal
- G01 - MEASURING TESTING
Information Patent Grant
Method for testing an integrated circuit device having elements wit...
- Patent number 7,500,164
- Issue date Mar 3, 2009
- International Business Machines Corporation
- Nathan P. Chelstrom
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
CIRCUIT DESIGN FOR BALANCED LOGIC STRESS
- Publication number 20150253807
- Publication date Sep 10, 2015
- International Business Machines Corporation
- Nathaniel R. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT DESIGN FOR BALANCED LOGIC STRESS
- Publication number 20150253808
- Publication date Sep 10, 2015
- International Business Machines Corporation
- Nathaniel R. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Isolating Failing Latches Using a Logic Built-In Self-Test
- Publication number 20140149814
- Publication date May 29, 2014
- International Business Machines Corporation
- Ra'ed M. Al-omari
- G01 - MEASURING TESTING
Information Patent Application
ON-CHIP DETECTION OF TYPES OF OPERATIONS TESTED BY AN LBIST
- Publication number 20140053034
- Publication date Feb 20, 2014
- International Business Machines Corporation
- Michael W. Harper
- G01 - MEASURING TESTING
Information Patent Application
ON-CHIP DETECTION OF TYPES OF OPERATIONS TESTED BY AN LBIST
- Publication number 20140053035
- Publication date Feb 20, 2014
- International Business Machines Corporation
- Michael W. Harper
- G01 - MEASURING TESTING
Information Patent Application
EVALUATION OF MULTIPLE INPUT SIGNATURE REGISTER RESULTS
- Publication number 20120084603
- Publication date Apr 5, 2012
- International Business Machines Corporation
- Mack Wayne Riley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Information Collection and Storage for Single Core Chips to 'N Core...
- Publication number 20100100357
- Publication date Apr 22, 2010
- International Business Machines Corporation
- Michael W. Harper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Structure For An Integrated Circuit That Employs Multiple Interfaces
- Publication number 20090222251
- Publication date Sep 3, 2009
- International Business Machines Corporation
- Tilman Gloekler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Maintaining Circuit Delay Characteristics During Power Management Mode
- Publication number 20090121747
- Publication date May 14, 2009
- Sang Hoo Dhong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Digital Thermal Sensor Test Implementation Without Using Main Core...
- Publication number 20090125267
- Publication date May 14, 2009
- Charles R. Johns
- G01 - MEASURING TESTING
Information Patent Application
Dynamic Frequency Scaling Sequence for Multi-Gigahertz Microprocessors
- Publication number 20090119552
- Publication date May 7, 2009
- Nathan Chelstrom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controlling Asynchronous Clock Domains to Perform Synchronous Opera...
- Publication number 20090106575
- Publication date Apr 23, 2009
- International Business Machines Corporation
- Nathan P. Chelstrom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Logic Built In Self Test (LBIST) Fault Det...
- Publication number 20090089636
- Publication date Apr 2, 2009
- Matthew E. Fernsler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Testing Functional Boundary Logic at Asynchronous Clock Boundaries...
- Publication number 20090083594
- Publication date Mar 26, 2009
- International Business Machines Corporation
- Nathan P. Chelstrom
- G01 - MEASURING TESTING
Information Patent Application
Method to Bridge a Distance Between eFuse Banks That Contain Encode...
- Publication number 20090058503
- Publication date Mar 5, 2009
- Michael Joseph Genden
- G11 - INFORMATION STORAGE
Information Patent Application
SECURE POWER-ON RESET ENGINE
- Publication number 20090055637
- Publication date Feb 26, 2009
- Ingemar Holm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
eFuse Programming Data Alignment Verification Apparatus and Method
- Publication number 20080320349
- Publication date Dec 25, 2008
- International Business Machines Corporation
- Mack W. Riley
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit to Reduce Transient Current Swings During Mode Transitions...
- Publication number 20080272820
- Publication date Nov 6, 2008
- International Business Machines Corporation
- David William Boerstler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Using eFuses to Store PLL Configuration Data
- Publication number 20080225566
- Publication date Sep 18, 2008
- International Business Machines Corporation
- Irene Beattie
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Controlling Asynchronous Clock Domains to Perform Synchronous Opera...
- Publication number 20080229136
- Publication date Sep 18, 2008
- International Business Machines Corporation
- Nathan P. Chelstrom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-use eFuse Macro
- Publication number 20080159010
- Publication date Jul 3, 2008
- Tarl S. Gordon
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR INTERFACING TO AN INTEGRATED CIRCUIT THAT...
- Publication number 20080147901
- Publication date Jun 19, 2008
- IBM Corporation
- Tilman Gloekler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High Speed On-Chip Serial Link Apparatus
- Publication number 20080133800
- Publication date Jun 5, 2008
- Tilman Gloekler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit to Reduce Power Supply Fluctuations in High Frequency/High...
- Publication number 20080133957
- Publication date Jun 5, 2008
- David William Boerstler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Method for Using a Single Bank of eFuses to Successiv...
- Publication number 20080104469
- Publication date May 1, 2008
- Mack Wayne Riley
- G11 - INFORMATION STORAGE
Information Patent Application
System and Method for Modifying a Test Pattern to Control Power Su...
- Publication number 20080082887
- Publication date Apr 3, 2008
- Sang H. Dhong
- G01 - MEASURING TESTING
Information Patent Application
System and Method for Advanced Logic Built-in Self Test with Select...
- Publication number 20080052579
- Publication date Feb 28, 2008
- Mack Wayne Riley
- G01 - MEASURING TESTING
Information Patent Application
System and Method for Reducing Test Time for Loading and Executing...
- Publication number 20080034261
- Publication date Feb 7, 2008
- Parag Birmiwal
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR TESTING AN INTEGRATED CIRCUIT DEVICE HAVING E...
- Publication number 20070283205
- Publication date Dec 6, 2007
- Nathan P. Chelstrom
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR TESTING FUNCTIONAL BOUNDARY LOGIC AT ASYNCHRO...
- Publication number 20070266284
- Publication date Nov 15, 2007
- Nathan P. Chelstrom
- G01 - MEASURING TESTING

Mack W. Riley

Person

Patents Grantslast 30 patents

Circuit design for balanced logic stress

Evaluation of multiple input signature register results

Circuit design for balanced logic stress

On-chip detection of types of operations tested by an LBIST

Isolating failing latches using a logic built-in self-test

Determining chip burn-in workload using emulated application condition

On-chip detection of types of operations tested by an LBIST

Information collection and storage for single core chips to 'N core...

Controlling asynchronous clock domains to perform synchronous opera...

Digital thermal sensor test implementation without using main core...

Testing functional boundary logic at asynchronous clock boundaries...

Secure power-on reset engine

Circuit to reduce transient current swings during mode transitions...

Circuit to reduce power supply fluctuations in high frequency/high...

Controlling asynchronous clock domains to perform synchronous opera...

eFuse programming data alignment verification

High speed on-chip serial link apparatus

Dynamic frequency scaling sequence for multi-gigahertz microprocessors

Using a single bank of efuses to successively store testing data fr...

Using eFuses to store PLL configuration data

Method to gate off PLLS in a deep power saving state without separa...

Clock control hierarchy for integrated microprocessors and systems-...

Method and apparatus for detecting frequency lock in a system inclu...

Modifying a test pattern to control power supply noise

Information handling system capable of detecting frequency lock of...

Apparatus and method for using eFuses to store PLL configuration data

System and method for advanced logic built-in self test with select...

Dynamic frequency scaling sequence for multi-gigahertz microprocessors

System and method for reducing test time for loading and executing...

Method for testing an integrated circuit device having elements wit...

Patents Applicationslast 30 patents

CIRCUIT DESIGN FOR BALANCED LOGIC STRESS

CIRCUIT DESIGN FOR BALANCED LOGIC STRESS

Isolating Failing Latches Using a Logic Built-In Self-Test

ON-CHIP DETECTION OF TYPES OF OPERATIONS TESTED BY AN LBIST

ON-CHIP DETECTION OF TYPES OF OPERATIONS TESTED BY AN LBIST

EVALUATION OF MULTIPLE INPUT SIGNATURE REGISTER RESULTS

Information Collection and Storage for Single Core Chips to 'N Core...

Structure For An Integrated Circuit That Employs Multiple Interfaces

Maintaining Circuit Delay Characteristics During Power Management Mode

Digital Thermal Sensor Test Implementation Without Using Main Core...

Dynamic Frequency Scaling Sequence for Multi-Gigahertz Microprocessors

Controlling Asynchronous Clock Domains to Perform Synchronous Opera...

Method and Apparatus for Logic Built In Self Test (LBIST) Fault Det...

Testing Functional Boundary Logic at Asynchronous Clock Boundaries...

Method to Bridge a Distance Between eFuse Banks That Contain Encode...

SECURE POWER-ON RESET ENGINE

eFuse Programming Data Alignment Verification Apparatus and Method

Circuit to Reduce Transient Current Swings During Mode Transitions...

Using eFuses to Store PLL Configuration Data

Controlling Asynchronous Clock Domains to Perform Synchronous Opera...

Multi-use eFuse Macro

METHOD AND APPARATUS FOR INTERFACING TO AN INTEGRATED CIRCUIT THAT...

High Speed On-Chip Serial Link Apparatus

Circuit to Reduce Power Supply Fluctuations in High Frequency/High...

Apparatus and Method for Using a Single Bank of eFuses to Successiv...

System and Method for Modifying a Test Pattern to Control Power Su...

System and Method for Advanced Logic Built-in Self Test with Select...

System and Method for Reducing Test Time for Loading and Executing...

SYSTEM AND METHOD FOR TESTING AN INTEGRATED CIRCUIT DEVICE HAVING E...

SYSTEM AND METHOD FOR TESTING FUNCTIONAL BOUNDARY LOGIC AT ASYNCHRO...