Madhumitra Sharma

Person

Shrewsbury, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cache coherency mechanism using arbitration masks
- Patent number 6,961,825
- Issue date Nov 1, 2005
- Hewlett-Packard Development Company, L.P.
- Simon C. Steely, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low latency inter-reference ordering in a multiple processor system...
- Patent number 6,904,465
- Issue date Jun 7, 2005
- Hewlett-Packard Development Company, L.P.
- Simon C. Steely, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Livelock prevention by delaying surrender of ownership upon interve...
- Patent number 6,801,986
- Issue date Oct 5, 2004
- Hewlett-Packard Development Company, L.P.
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for selectively imposing interference order between page-...
- Patent number 6,286,090
- Issue date Sep 4, 2001
- Compaq Computer Corporation
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shadow commands to optimize sequencing of requests in a switch-base...
- Patent number 6,279,084
- Issue date Aug 21, 2001
- Compaq Computer Corporation
- Stephen R. VanDoren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-performance non-blocking switch with multiple channel ordering...
- Patent number 6,249,520
- Issue date Jun 19, 2001
- Compaq Computer Corporation
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for optimizing generation of commit-signals in a distribu...
- Patent number 6,209,065
- Issue date Mar 27, 2001
- Compaq Computer Corporation
- Stephen R. Van Doren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victimization of clean data blocks
- Patent number 6,202,126
- Issue date Mar 13, 2001
- Compaq Computer Corporation
- Stephen Van Doren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low occupancy protocol for managing concurrent transactions with de...
- Patent number 6,154,816
- Issue date Nov 28, 2000
- Compaq Computer Corp.
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Order supporting mechanisms for use in a switch-based multi-process...
- Patent number 6,122,714
- Issue date Sep 19, 2000
- Compaq Computer Corp.
- Stephen R. VanDoren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing latency of inter-reference orderi...
- Patent number 6,108,737
- Issue date Aug 22, 2000
- Compaq Computer Corporation
- Madhumitra Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for disambiguating change-to-dirty commands in...
- Patent number 6,101,420
- Issue date Aug 8, 2000
- Compaq Computer Corporation
- Stephen R. VanDoren
- G05 - CONTROLLING REGULATING
Information Patent Grant
Multi-processor system for transferring data without incurring dead...
- Patent number 6,094,686
- Issue date Jul 25, 2000
- Compaq Computer Corporation
- Madhumitra Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for reducing latency of memory barrier operations on a mu...
- Patent number 6,088,771
- Issue date Jul 11, 2000
- Digital Equipment Corporation
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for employing commit-signals and prefetching t...
- Patent number 6,085,263
- Issue date Jul 4, 2000
- Compaq Computer Corp.
- Madhumitra Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-processor computer system having a data switch with simultane...
- Patent number 6,085,276
- Issue date Jul 4, 2000
- Compaq Computers Corporation
- Stephen R. VanDoren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique for reducing latency of inter-reference ordering using co...
- Patent number 6,055,605
- Issue date Apr 25, 2000
- Compaq Computer Corporation
- Madhumitra Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Employing multiple channels for deadlock avoidance in a cache coher...
- Patent number 6,014,690
- Issue date Jan 11, 2000
- Digital Equipment Corporation
- Stephen R. VanDoren
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Mechanism for packet component merging and channel assignment, and...
- Publication number 20030076831
- Publication date Apr 24, 2003
- Stephen R. Van Doren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for ownership load locked misses for atomic lo...
- Publication number 20030037223
- Publication date Feb 20, 2003
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low latency inter-reference ordering in a multiple processor system...
- Publication number 20020194290
- Publication date Dec 19, 2002
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Always succeeding change to dirty method
- Publication number 20020152358
- Publication date Oct 17, 2002
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Credit-based flow control technique in a modular multiprocessor system
- Publication number 20020146022
- Publication date Oct 10, 2002
- Stephen R. Van Doren
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Cache coherency mechanism using arbitration masks
- Publication number 20020099833
- Publication date Jul 25, 2002
- Simon C. Steely
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multicast decomposition mechanism in a hierarchically order distrib...
- Publication number 20020009095
- Publication date Jan 24, 2002
- Stephen R. Van Doren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Initiate flow control mechanism of a modular multiprocessor system
- Publication number 20010055277
- Publication date Dec 27, 2001
- Simon C. Steely
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Madhumitra Sharma

Person

Patents Grantslast 30 patents

Cache coherency mechanism using arbitration masks

Low latency inter-reference ordering in a multiple processor system...

Livelock prevention by delaying surrender of ownership upon interve...

Mechanism for selectively imposing interference order between page-...

Shadow commands to optimize sequencing of requests in a switch-base...

High-performance non-blocking switch with multiple channel ordering...

Mechanism for optimizing generation of commit-signals in a distribu...

Victimization of clean data blocks

Low occupancy protocol for managing concurrent transactions with de...

Order supporting mechanisms for use in a switch-based multi-process...

Method and apparatus for reducing latency of inter-reference orderi...

Method and apparatus for disambiguating change-to-dirty commands in...

Multi-processor system for transferring data without incurring dead...

Mechanism for reducing latency of memory barrier operations on a mu...

Method and apparatus for employing commit-signals and prefetching t...

Multi-processor computer system having a data switch with simultane...

Technique for reducing latency of inter-reference ordering using co...

Employing multiple channels for deadlock avoidance in a cache coher...

Patents Applicationslast 30 patents

Mechanism for packet component merging and channel assignment, and...

Apparatus and method for ownership load locked misses for atomic lo...

Low latency inter-reference ordering in a multiple processor system...

Always succeeding change to dirty method

Credit-based flow control technique in a modular multiprocessor system

Cache coherency mechanism using arbitration masks

Multicast decomposition mechanism in a hierarchically order distrib...

Initiate flow control mechanism of a modular multiprocessor system