Mahesh Dandapani IYER

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamically scalable timing and power models for programmable logic...
- Patent number 12,273,107
- Issue date Apr 8, 2025
- Altera Corporation
- Atul Maheshwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage regulator circuit systems and methods
- Patent number 12,253,870
- Issue date Mar 18, 2025
- Altera Corporation
- Archanna Srinivasan
- G05 - CONTROLLING REGULATING
Information Patent Grant
Circuit systems and methods for reducing power supply voltage droop
- Patent number 12,255,648
- Issue date Mar 18, 2025
- Altera Corporation
- Archanna Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
On-die aging measurements for dynamic timing modeling
- Patent number 12,216,150
- Issue date Feb 4, 2025
- Altera Corporation
- Dheeraj Subbareddy
- G01 - MEASURING TESTING
Information Patent Grant
Fast memory for programmable devices
- Patent number 12,003,238
- Issue date Jun 4, 2024
- Intel Corporation
- Scott Jeremy Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three dimensional circuit systems and methods having memory hierarc...
- Patent number 11,789,641
- Issue date Oct 17, 2023
- Intel Corporation
- Scott Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-die aging measurements for dynamic timing modeling
- Patent number 11,609,262
- Issue date Mar 21, 2023
- Intel Corporation
- Dheeraj Subbareddy
- G01 - MEASURING TESTING
Information Patent Grant
Techniques for providing optimizations based on categories of slack...
- Patent number 11,574,101
- Issue date Feb 7, 2023
- Intel Corporation
- Scott Whitty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three dimensional programmable logic circuit systems and methods
- Patent number 11,489,527
- Issue date Nov 1, 2022
- Intel Corporation
- Scott Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for handling integrated circuit dies with defects
- Patent number 11,368,158
- Issue date Jun 21, 2022
- Intel Corporation
- Dheeraj Subbareddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for reducing reliability degradation on an in...
- Patent number 11,113,442
- Issue date Sep 7, 2021
- Intel Corporation
- Ning Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast memory for programmable devices
- Patent number 11,101,804
- Issue date Aug 24, 2021
- Intel Corporation
- Scott Jeremy Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatus to insert buffers in a dataflow graph
- Patent number 10,965,536
- Issue date Mar 30, 2021
- Intel Corporation
- Kermin E. ChoFleming
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods for incremental circuit physical synthesis
- Patent number 10,936,772
- Issue date Mar 2, 2021
- Altera Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing rewind structural verification...
- Patent number 10,922,461
- Issue date Feb 16, 2021
- Intel Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for verifying initial state equivalence of cha...
- Patent number 10,706,203
- Issue date Jul 7, 2020
- Altera Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process for preparing a paraffin product
- Patent number 10,669,486
- Issue date Jun 2, 2020
- Shell Oil Company
- Gerald Sprachmann
- C01 - INORGANIC CHEMISTRY
Information Patent Grant
Method and apparatus for verifying structural correctness in retime...
- Patent number 10,671,790
- Issue date Jun 2, 2020
- Altera Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for signal skew compensation
- Patent number 10,523,224
- Issue date Dec 31, 2019
- Altera Corporation
- David Mendel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for reducing constraints during rewind structu...
- Patent number 10,489,535
- Issue date Nov 26, 2019
- Intel Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing register retiming by utilizing...
- Patent number 10,417,374
- Issue date Sep 17, 2019
- Altera Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable low memory modes for reduced power consumption
- Patent number 10,409,513
- Issue date Sep 10, 2019
- QUALCOMM Incorporated
- Gabriel Allen Watkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Discretizing gate sizes during numerical synthesis
- Patent number 10,394,993
- Issue date Aug 27, 2019
- Synopsys, Inc.
- Amir H. Mottaez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for verifying retimed circuits with delayed initialization
- Patent number 10,372,850
- Issue date Aug 6, 2019
- Intel Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for bounding the number of delayed reset clock cycles for r...
- Patent number 10,354,038
- Issue date Jul 16, 2019
- Intel Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process for preparing a paraffin product
- Patent number 10,351,780
- Issue date Jul 16, 2019
- Shell Oil Company
- Gerald Sprachmann
- C10 - PETROLEUM, GAS OR COKE INDUSTRIES TECHNICAL GASES CONTAINING CARBON MON...
Information Patent Grant
Methods for incremental circuit design legalization during physical...
- Patent number 10,339,241
- Issue date Jul 2, 2019
- Altera Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for signal skew compensation
- Patent number 10,333,535
- Issue date Jun 25, 2019
- Altera Corporation
- David Mendel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods for reducing delay on integrated circuits by identifying ca...
- Patent number 10,318,686
- Issue date Jun 11, 2019
- Intel Corporation
- Shounak Dhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing clock allocation for a system i...
- Patent number 10,303,202
- Issue date May 28, 2019
- Altera Corporation
- Saurabh Adya
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FPGA Compiler Flow for Heterogeneous Programmable Logic Elements
- Publication number 20240184966
- Publication date Jun 6, 2024
- Babette Van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fast CAD Compilation Through Coarse Macro Lowering
- Publication number 20240020449
- Publication date Jan 18, 2024
- Intel Corporation
- Byron Sinclair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST FPGA COMPILATION THROUGH BITSTREAM STITCHING
- Publication number 20230333826
- Publication date Oct 19, 2023
- Michael Kinsner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modular Compilation Flows for a Programmable Logic Device
- Publication number 20230237231
- Publication date Jul 27, 2023
- Intel Corporation
- Byron Sinclair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST FPGA COMPILATION FROM SOFTWARE FLOWS THROUGH PARTIAL RECONFIGU...
- Publication number 20230237230
- Publication date Jul 27, 2023
- Intel Corporation
- Michael Kinsner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems And Methods For Correcting Errors in Code For Circuit Designs
- Publication number 20230222275
- Publication date Jul 13, 2023
- Intel Corporation
- Gregg Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On-Die Aging Measurements for Dynamic Timing Modeling
- Publication number 20230129176
- Publication date Apr 27, 2023
- Intel Corporation
- Dheeraj Subbareddy
- G01 - MEASURING TESTING
Information Patent Application
Power Savings by Register Insertion in Large Combinational Circuits
- Publication number 20230027064
- Publication date Jan 26, 2023
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Backside Metallization for FPGA Resources
- Publication number 20230024515
- Publication date Jan 26, 2023
- Atul Maheshwari
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Retiming and Overclocking of Large Circuits
- Publication number 20230018414
- Publication date Jan 19, 2023
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Three Dimensional Circuit Systems And Methods Having Memory Hierarc...
- Publication number 20220405005
- Publication date Dec 22, 2022
- Intel Corporation
- Scott Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR PROGRAMMABLE FABRIC DESIGN COMPILATION
- Publication number 20220335189
- Publication date Oct 20, 2022
- Yi Peng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Temperature Control Systems And Methods For Integrated Circuits
- Publication number 20220215147
- Publication date Jul 7, 2022
- Intel Corporation
- Teik Wah Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamically Scalable Timing and Power Models for Programmable Logic...
- Publication number 20220116042
- Publication date Apr 14, 2022
- Intel Corporation
- Atul Maheshwari
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Power Allocation using Multiple Voltage Domains for Programmable Lo...
- Publication number 20220116045
- Publication date Apr 14, 2022
- Intel Corporation
- Mahesh K. Kumashikar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adjustable Integrated Circuit Operation Using Power Headroom
- Publication number 20220113788
- Publication date Apr 14, 2022
- Mahesh K. Kumashikar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS TO REDUCE VOLTAGE GUARDBAND
- Publication number 20220113694
- Publication date Apr 14, 2022
- Intel Corporation
- Mahesh K. Kumashikar
- G05 - CONTROLLING REGULATING
Information Patent Application
SWITCH BASED ON LOAD CURRENT
- Publication number 20220115959
- Publication date Apr 14, 2022
- Intel Corporation
- MD Altaf Hossain
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
DYNAMIC LOADLINES FOR PROGRAMMABLE FABRIC DEVICES
- Publication number 20220114316
- Publication date Apr 14, 2022
- Intel Corporation
- Yuet Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controlled Transition Between Configuration Mode and User Mode to R...
- Publication number 20220113756
- Publication date Apr 14, 2022
- Intel Corporation
- Atul Maheshwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Management using Voltage Islands on Programmable Logic Devices
- Publication number 20220116041
- Publication date Apr 14, 2022
- Mahesh K. Kumashikar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Circuits And Methods For Accessing Signals In Integrated Circuits
- Publication number 20220077856
- Publication date Mar 10, 2022
- Intel Corporation
- Yi Peng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems And Methods For Circuit Design Dependent Programmable Maxim...
- Publication number 20220004688
- Publication date Jan 6, 2022
- Intel Corporation
- Archanna Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST MEMORY FOR PROGRAMMABLE DEVICES
- Publication number 20210384912
- Publication date Dec 9, 2021
- Intel Corporation
- Scott Jeremy Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS FOR REDUCING RELIABILITY DEGRADATION ON AN IN...
- Publication number 20210383049
- Publication date Dec 9, 2021
- Intel Corporation
- Ning Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Three Dimensional Programmable Logic Circuit Systems And Methods
- Publication number 20210313988
- Publication date Oct 7, 2021
- Intel Corporation
- Scott Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Circuit Systems And Methods For Reducing Power Supply Voltage Droop
- Publication number 20210313991
- Publication date Oct 7, 2021
- Intel Corporation
- Archanna Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Voltage Regulator Circuit Systems And Methods
- Publication number 20210311517
- Publication date Oct 7, 2021
- Intel Corporation
- Archanna Srinivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Supply Voltage Control Systems And Methods For Integrated Circuits
- Publication number 20210311537
- Publication date Oct 7, 2021
- Intel Corporation
- Archanna Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques For Providing Optimizations Based On Categories Of Slack...
- Publication number 20210216692
- Publication date Jul 15, 2021
- Intel Corporation
- Scott Whitty
- G06 - COMPUTING CALCULATING COUNTING

Mahesh Dandapani IYER

Person

Patents Grantslast 30 patents

Dynamically scalable timing and power models for programmable logic...

Voltage regulator circuit systems and methods

Circuit systems and methods for reducing power supply voltage droop

On-die aging measurements for dynamic timing modeling

Fast memory for programmable devices

Three dimensional circuit systems and methods having memory hierarc...

On-die aging measurements for dynamic timing modeling

Techniques for providing optimizations based on categories of slack...

Three dimensional programmable logic circuit systems and methods

Methods for handling integrated circuit dies with defects

Methods and apparatus for reducing reliability degradation on an in...

Fast memory for programmable devices

Methods and apparatus to insert buffers in a dataflow graph

Methods for incremental circuit physical synthesis

Method and apparatus for performing rewind structural verification...

Method and apparatus for verifying initial state equivalence of cha...

Process for preparing a paraffin product

Method and apparatus for verifying structural correctness in retime...

Techniques for signal skew compensation

Method and apparatus for reducing constraints during rewind structu...

Method and apparatus for performing register retiming by utilizing...

Configurable low memory modes for reduced power consumption

Discretizing gate sizes during numerical synthesis

Methods for verifying retimed circuits with delayed initialization

Methods for bounding the number of delayed reset clock cycles for r...

Process for preparing a paraffin product

Methods for incremental circuit design legalization during physical...

Techniques for signal skew compensation

Methods for reducing delay on integrated circuits by identifying ca...

Method and apparatus for performing clock allocation for a system i...

Patents Applicationslast 30 patents

FPGA Compiler Flow for Heterogeneous Programmable Logic Elements

Fast CAD Compilation Through Coarse Macro Lowering

FAST FPGA COMPILATION THROUGH BITSTREAM STITCHING

Modular Compilation Flows for a Programmable Logic Device

FAST FPGA COMPILATION FROM SOFTWARE FLOWS THROUGH PARTIAL RECONFIGU...

Systems And Methods For Correcting Errors in Code For Circuit Designs

On-Die Aging Measurements for Dynamic Timing Modeling

Power Savings by Register Insertion in Large Combinational Circuits

Backside Metallization for FPGA Resources

Retiming and Overclocking of Large Circuits

Three Dimensional Circuit Systems And Methods Having Memory Hierarc...

SYSTEMS AND METHODS FOR PROGRAMMABLE FABRIC DESIGN COMPILATION

Temperature Control Systems And Methods For Integrated Circuits

Dynamically Scalable Timing and Power Models for Programmable Logic...

Power Allocation using Multiple Voltage Domains for Programmable Lo...

Adjustable Integrated Circuit Operation Using Power Headroom

SYSTEMS AND METHODS TO REDUCE VOLTAGE GUARDBAND

SWITCH BASED ON LOAD CURRENT

DYNAMIC LOADLINES FOR PROGRAMMABLE FABRIC DEVICES

Controlled Transition Between Configuration Mode and User Mode to R...

Power Management using Voltage Islands on Programmable Logic Devices

Circuits And Methods For Accessing Signals In Integrated Circuits

Systems And Methods For Circuit Design Dependent Programmable Maxim...

FAST MEMORY FOR PROGRAMMABLE DEVICES

METHODS AND APPARATUS FOR REDUCING RELIABILITY DEGRADATION ON AN IN...

Three Dimensional Programmable Logic Circuit Systems And Methods

Circuit Systems And Methods For Reducing Power Supply Voltage Droop

Voltage Regulator Circuit Systems And Methods

Supply Voltage Control Systems And Methods For Integrated Circuits

Techniques For Providing Optimizations Based On Categories Of Slack...