Mahesh Madhav

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Reservation architecture for overcommitted memory
- Patent number 11,681,611
- Issue date Jun 20, 2023
- Intel Corporation
- Omid Azizi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware-assisted paging mechanisms
- Patent number 11,392,491
- Issue date Jul 19, 2022
- Intel Corporation
- Amin Firoozshahian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pause communication from I/O devices supporting page faults
- Patent number 11,169,929
- Issue date Nov 9, 2021
- Intel Corporation
- Rupin Vakharwala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reservation architecture for overcommitted memory
- Patent number 10,866,888
- Issue date Dec 15, 2020
- Intel Corporation
- Omid Azizi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical page tracking for handling overcommitted memory
- Patent number 10,733,108
- Issue date Aug 4, 2020
- Intel Corporation
- Vijay Bahirji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory pressure notifier
- Patent number 10,579,551
- Issue date Mar 3, 2020
- Intel Corporation
- Ishwar Agarwal
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
RUNTIME ADAPTIVE PREFETCHING IN A MANY-CORE SYSTEM
- Publication number 20240354110
- Publication date Oct 24, 2024
- Ampere Computing LLC
- Erika Susana ALCORTA LOZANO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TRAINED SCALABLE PREFETCHER, AND RELATED METHODS
- Publication number 20240232090
- Publication date Jul 11, 2024
- Ampere Computing LLC
- Benjamin Crawford Chaffin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LATENCY-AWARE PREFETCH BUFFER
- Publication number 20220197807
- Publication date Jun 23, 2022
- Ampere Computing LLC
- Jonathan Christopher Perry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESERVATION ARCHITECTURE FOR OVERCOMMITTED MEMORY
- Publication number 20210240609
- Publication date Aug 5, 2021
- Intel Corporation
- Omid Azizi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE-ASSISTED PAGING MECHANISMS
- Publication number 20200004677
- Publication date Jan 2, 2020
- Intel Corporation
- Amin Firoozshahian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHYSICAL PAGE TRACKING FOR HANDLING OVERCOMMITTED MEMORY
- Publication number 20190354487
- Publication date Nov 21, 2019
- Vijay Bahirji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SURVIVABILITY GUARANTEES FOR MEMORY TRAFFIC
- Publication number 20190303281
- Publication date Oct 3, 2019
- Amin Firoozshahian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESERVATION ARCHITECTURE FOR OVERCOMMITTED MEMORY
- Publication number 20190213120
- Publication date Jul 11, 2019
- Omid Azizi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PRESSURE NOTIFIER
- Publication number 20190196988
- Publication date Jun 27, 2019
- Intel Corporation
- Ishwar Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PAUSE COMMUNICATION FROM I/O DEVICES SUPPORTING PAGE FAULTS
- Publication number 20190042461
- Publication date Feb 7, 2019
- Rupin Vakharwala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS TO EFFICIENTLY GENERATE A PROCESSOR ARCHITECTU...
- Publication number 20110153529
- Publication date Jun 23, 2011
- Anne W. Bracy
- G06 - COMPUTING CALCULATING COUNTING

Mahesh Madhav

Person

Patents Grantslast 30 patents

Reservation architecture for overcommitted memory

Hardware-assisted paging mechanisms

Pause communication from I/O devices supporting page faults

Reservation architecture for overcommitted memory

Physical page tracking for handling overcommitted memory

Memory pressure notifier

Patents Applicationslast 30 patents

RUNTIME ADAPTIVE PREFETCHING IN A MANY-CORE SYSTEM

MULTI-TRAINED SCALABLE PREFETCHER, AND RELATED METHODS

LATENCY-AWARE PREFETCH BUFFER

RESERVATION ARCHITECTURE FOR OVERCOMMITTED MEMORY

HARDWARE-ASSISTED PAGING MECHANISMS

PHYSICAL PAGE TRACKING FOR HANDLING OVERCOMMITTED MEMORY

SURVIVABILITY GUARANTEES FOR MEMORY TRAFFIC

RESERVATION ARCHITECTURE FOR OVERCOMMITTED MEMORY

MEMORY PRESSURE NOTIFIER

PAUSE COMMUNICATION FROM I/O DEVICES SUPPORTING PAGE FAULTS

METHOD AND APPARATUS TO EFFICIENTLY GENERATE A PROCESSOR ARCHITECTU...