Mahesh Ramdas Vasishta

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Bangalore, IN

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Patents Grantslast 30 patents

Information Patent Grant
Low clock-power integrated clock gating cell
- Patent number 9,362,910
- Issue date Jun 7, 2016
- Texas Instruments Incorporated
- Girishankar Gurumurthy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High density flip-flop with asynchronous reset
- Patent number 8,578,224
- Issue date Nov 5, 2013
- Texas Instruments Incorporated
- Girishankar Gurumurthy
- G01 - MEASURING TESTING
Information Patent Grant
Functional-input sequential circuit
- Patent number 7,825,689
- Issue date Nov 2, 2010
- Texas Instruments Incorporated
- Mahesh Ramdas Vasishta
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
LOW POWER CLOCK GATED FLIP-FLOPS
- Publication number 20150070063
- Publication date Mar 12, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Girishankar Gurumurthy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW CLOCK-POWER INTEGRATED CLOCK GATING CELL
- Publication number 20140184271
- Publication date Jul 3, 2014
- Girishankar Gurumurthy
- H03 - BASIC ELECTRONIC CIRCUITRY