Mahesh Wagh

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Logical physical layer interface specification support for PCie 6.0...
- Patent number 12,222,881
- Issue date Feb 11, 2025
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for synchronizing multiple virtual lin...
- Patent number 12,001,353
- Issue date Jun 4, 2024
- Intel Corporation
- Joon Teik Hor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link layer-PHY interface adapter
- Patent number 11,971,841
- Issue date Apr 30, 2024
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multichip package link error detection
- Patent number 11,797,378
- Issue date Oct 24, 2023
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to support multiple protocols between computer system in...
- Patent number 11,729,096
- Issue date Aug 15, 2023
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flex bus protocol negotiation and enabling sequence
- Patent number 11,726,939
- Issue date Aug 15, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtualized link states of multiple protocol layer package intercon...
- Patent number 11,663,154
- Issue date May 30, 2023
- Intel Corporation
- Joon Teik Hor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for synchronizing multiple virtual lin...
- Patent number 11,442,876
- Issue date Sep 13, 2022
- Intel Corporation
- Joon Teik Hor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extending multichip package link off package
- Patent number 11,386,033
- Issue date Jul 12, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multichip package link error detection
- Patent number 11,307,928
- Issue date Apr 19, 2022
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtualized link states of multiple protocol layer package intercon...
- Patent number 11,308,018
- Issue date Apr 19, 2022
- Intel Corporation
- Joon Teik Hor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to support multiple interconnect protocols for a common...
- Patent number 11,245,604
- Issue date Feb 8, 2022
- Intel Corporation
- Mahesh Wagh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flex bus protocol negotiation and enabling sequence
- Patent number 11,144,492
- Issue date Oct 12, 2021
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extending multichip package link off package
- Patent number 11,113,225
- Issue date Sep 7, 2021
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to support multiple protocols between computer system in...
- Patent number 11,095,556
- Issue date Aug 17, 2021
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multichip package link error detection
- Patent number 11,061,761
- Issue date Jul 13, 2021
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multichip package link
- Patent number 11,003,610
- Issue date May 11, 2021
- Intel Corporation
- Zuoguo Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to support multiple interconnect protocols for a common...
- Patent number 10,884,195
- Issue date Jan 5, 2021
- Intel Corporation
- Mahesh Wagh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated input/output management
- Patent number 10,860,515
- Issue date Dec 8, 2020
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage modulated control lane
- Patent number 10,846,258
- Issue date Nov 24, 2020
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtualized link states of multiple protocol layer package intercon...
- Patent number 10,776,302
- Issue date Sep 15, 2020
- Intel Corporation
- Joon Teik Hor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extending multichip package link off package
- Patent number 10,678,736
- Issue date Jun 9, 2020
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flex bus protocol negotiation and enabling sequence
- Patent number 10,606,785
- Issue date Mar 31, 2020
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus, system for centering in a high performance inter...
- Patent number 10,560,081
- Issue date Feb 11, 2020
- Intel Corporation
- Mahesh Wagh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multichip package link error detection
- Patent number 10,552,253
- Issue date Feb 4, 2020
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multichip package link
- Patent number 10,552,357
- Issue date Feb 4, 2020
- Intel Corporation
- Zuoguo J. Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Valid lane training
- Patent number 10,461,805
- Issue date Oct 29, 2019
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for software defined interconnect switch
- Patent number 10,191,877
- Issue date Jan 29, 2019
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device, system and method for communication with heterogeneous phys...
- Patent number 10,180,927
- Issue date Jan 15, 2019
- Intel Corporation
- Akshay G. Pethe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link-physical layer interface adapter
- Patent number 10,152,446
- Issue date Dec 11, 2018
- Intel Corporation
- Venkatraman Iyer
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
LINK LAYER-PHY INTERFACE ADAPTER
- Publication number 20250013600
- Publication date Jan 9, 2025
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE
- Publication number 20240020259
- Publication date Jan 18, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE
- Publication number 20230073807
- Publication date Mar 9, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Synchronizing Multiple Virtual Lin...
- Publication number 20230026906
- Publication date Jan 26, 2023
- Intel Corporation
- Joon Teik Hor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICHIP PACKAGE LINK ERROR DETECTION
- Publication number 20220350698
- Publication date Nov 3, 2022
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUALIZED LINK STATES OF MULTIPLE PROTOCOL LAYER PACKAGE INTERCON...
- Publication number 20220350769
- Publication date Nov 3, 2022
- Intel Corporation
- Joon Teik Hor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEX BUS PROTOCOL NEGOTIATION AND ENABLING SEQUENCE
- Publication number 20220012203
- Publication date Jan 13, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO SUPPORT MULTIPLE PROTOCOLS BETWEEN COMPUTER SYSTEM IN...
- Publication number 20210399982
- Publication date Dec 23, 2021
- Intel Corporation
- DEBENDRA DAS SHARMA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LOGICAL PHYSICAL LAYER INTERFACE SPECIFICATION SUPPORT FOR PCIE 6.0...
- Publication number 20210232520
- Publication date Jul 29, 2021
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO SUPPORT MULTIPLE INTERCONNECT PROTOCOLS FOR A COMMON...
- Publication number 20210109300
- Publication date Apr 15, 2021
- Intel Corporation
- MAHESH WAGH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, APPARATUS AND METHOD FOR HANDLING MULTI-PROTOCOL TRAFFIC IN...
- Publication number 20210112132
- Publication date Apr 15, 2021
- NITISH PALIWAL
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE
- Publication number 20210097015
- Publication date Apr 1, 2021
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latency-Optimized Mechanisms for Handling Errors or Mis-Routed Pack...
- Publication number 20210013999
- Publication date Jan 14, 2021
- Intel Corporation
- Swadesh Choudhary
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE
- Publication number 20200409896
- Publication date Dec 31, 2020
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUALIZED LINK STATES OF MULTIPLE PROTOCOL LAYER PACKAGE INTERCON...
- Publication number 20200409899
- Publication date Dec 31, 2020
- Intel Corporation
- Joon Teik Hor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK LAYER-PHY INTERFACE ADAPTER
- Publication number 20200394150
- Publication date Dec 17, 2020
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICHIP PACKAGE LINK ERROR DETECTION
- Publication number 20200356436
- Publication date Nov 12, 2020
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICHIP PACKAGE LINK
- Publication number 20200320031
- Publication date Oct 8, 2020
- Intel Corporation
- Zuoguo Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICHIP PACKAGE LINK ERROR DETECTION
- Publication number 20200319957
- Publication date Oct 8, 2020
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAM IDENTIFIER LANE PROTECTION
- Publication number 20200244397
- Publication date Jul 30, 2020
- Intel Corporation
- Venkatraman Iyer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
FLEX BUS PROTOCOL NEGOTIATION AND ENABLING SEQUENCE
- Publication number 20200210366
- Publication date Jul 2, 2020
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Synchronizing Multiple Virtual Lin...
- Publication number 20190347218
- Publication date Nov 14, 2019
- Joon Teik Hor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VALID LANE TRAINING
- Publication number 20190238179
- Publication date Aug 1, 2019
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUALIZED LINK STATES OF MULTIPLE PROTOCOL LAYER PACKAGE INTERCON...
- Publication number 20190227972
- Publication date Jul 25, 2019
- Intel Corporation
- Joon Teik Hor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEX BUS PROTOCOL NEGOTIATION AND ENABLING SEQUENCE
- Publication number 20190065426
- Publication date Feb 28, 2019
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED INPUT/OUTPUT MANAGEMENT
- Publication number 20190050362
- Publication date Feb 14, 2019
- Intel Corporation
- Swadesh CHOUDHARY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO SUPPORT MULTIPLE PROTOCOLS BETWEEN COMPUTER SYSTEM IN...
- Publication number 20190007310
- Publication date Jan 3, 2019
- Intel Corporation
- DEBENDRA DAS SHARMA
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MULTICHIP PACKAGE LINK
- Publication number 20180300275
- Publication date Oct 18, 2018
- Intel Corporation
- Zuoguo J. Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE
- Publication number 20180276164
- Publication date Sep 27, 2018
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multichip Package Link Error Detection
- Publication number 20180196710
- Publication date Jul 12, 2018
- Intel Corporation
- Venkatraman Iyer
- G06 - COMPUTING CALCULATING COUNTING

Mahesh Wagh

Person

Patents Grantslast 30 patents

Logical physical layer interface specification support for PCie 6.0...

System, apparatus and method for synchronizing multiple virtual lin...

Link layer-PHY interface adapter

Multichip package link error detection

Techniques to support multiple protocols between computer system in...

Flex bus protocol negotiation and enabling sequence

Virtualized link states of multiple protocol layer package intercon...

System, apparatus and method for synchronizing multiple virtual lin...

Extending multichip package link off package

Multichip package link error detection

Virtualized link states of multiple protocol layer package intercon...

Techniques to support multiple interconnect protocols for a common...

Flex bus protocol negotiation and enabling sequence

Extending multichip package link off package

Techniques to support multiple protocols between computer system in...

Multichip package link error detection

Multichip package link

Techniques to support multiple interconnect protocols for a common...

Integrated input/output management

Voltage modulated control lane

Virtualized link states of multiple protocol layer package intercon...

Extending multichip package link off package

Flex bus protocol negotiation and enabling sequence

Method, apparatus, system for centering in a high performance inter...

Multichip package link error detection

Multichip package link

Valid lane training

Architecture for software defined interconnect switch

Device, system and method for communication with heterogeneous phys...

Link-physical layer interface adapter

Patents Applicationslast 30 patents

LINK LAYER-PHY INTERFACE ADAPTER

EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE

EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE

System, Apparatus And Method For Synchronizing Multiple Virtual Lin...

MULTICHIP PACKAGE LINK ERROR DETECTION

VIRTUALIZED LINK STATES OF MULTIPLE PROTOCOL LAYER PACKAGE INTERCON...

FLEX BUS PROTOCOL NEGOTIATION AND ENABLING SEQUENCE

TECHNIQUES TO SUPPORT MULTIPLE PROTOCOLS BETWEEN COMPUTER SYSTEM IN...

LOGICAL PHYSICAL LAYER INTERFACE SPECIFICATION SUPPORT FOR PCIE 6.0...

TECHNIQUES TO SUPPORT MULTIPLE INTERCONNECT PROTOCOLS FOR A COMMON...

SYSTEM, APPARATUS AND METHOD FOR HANDLING MULTI-PROTOCOL TRAFFIC IN...

EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE

Latency-Optimized Mechanisms for Handling Errors or Mis-Routed Pack...

EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE

VIRTUALIZED LINK STATES OF MULTIPLE PROTOCOL LAYER PACKAGE INTERCON...

LINK LAYER-PHY INTERFACE ADAPTER

MULTICHIP PACKAGE LINK ERROR DETECTION

MULTICHIP PACKAGE LINK

MULTICHIP PACKAGE LINK ERROR DETECTION

STREAM IDENTIFIER LANE PROTECTION

FLEX BUS PROTOCOL NEGOTIATION AND ENABLING SEQUENCE

System, Apparatus And Method For Synchronizing Multiple Virtual Lin...

VALID LANE TRAINING

VIRTUALIZED LINK STATES OF MULTIPLE PROTOCOL LAYER PACKAGE INTERCON...

FLEX BUS PROTOCOL NEGOTIATION AND ENABLING SEQUENCE

INTEGRATED INPUT/OUTPUT MANAGEMENT

TECHNIQUES TO SUPPORT MULTIPLE PROTOCOLS BETWEEN COMPUTER SYSTEM IN...

MULTICHIP PACKAGE LINK

EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE

Multichip Package Link Error Detection