Majid Aghababazadeh

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Contactless technique for evaluating a fabrication of a wafer
- Patent number 8,990,759
- Issue date Mar 24, 2015
- tau-Metrix, Inc.
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Grant
Integrated photodiode for semiconductor substrates
- Patent number 8,872,297
- Issue date Oct 28, 2014
- tau-Metrix, Inc.
- Gary Steinbrueck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated photodiode for semiconductor substrates
- Patent number 8,410,568
- Issue date Apr 2, 2013
- tau-Metrix, Inc.
- Gary Steinbrueck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structures for evaluating a fabrication of a die or a wafer
- Patent number 8,344,745
- Issue date Jan 1, 2013
- tau-Metrix, Inc.
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Grant
System and apparatus for using test structures inside of a chip dur...
- Patent number 7,736,916
- Issue date Jun 15, 2010
- tau-Metrix, Inc.
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Grant
Contactless technique for evaluating a fabrication of a wafer
- Patent number 7,730,434
- Issue date Jun 1, 2010
- tau-Metrix, Inc.
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Grant
System for using test structures to evaluate a fabrication of a wafer
- Patent number 7,723,724
- Issue date May 25, 2010
- tau-Metrix, Inc.
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Grant
Intra-chip power and test signal generation for use with test struc...
- Patent number 7,605,597
- Issue date Oct 20, 2009
- tau-Metrix, Inc.
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Grant
Technique for evaluating a fabrication of a die and wafer
- Patent number 7,423,288
- Issue date Sep 9, 2008
- tau-Metrix, Inc.
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Grant
Intra-clip power and test signal generation for use with test struc...
- Patent number 7,339,388
- Issue date Mar 4, 2008
- tau-Metrix, Inc.
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Grant
System and apparatus for using test structures inside of a chip dur...
- Patent number 7,256,055
- Issue date Aug 14, 2007
- tau-Metrix, Inc.
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Grant
Technique for evaluating a fabrication of a die and wafer
- Patent number 7,220,990
- Issue date May 22, 2007
- tau-Metrix, Inc.
- Majid Aghababazadeh
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED PHOTODIODE FOR SEMICONDUCTOR SUBSTRATES
- Publication number 20160104812
- Publication date Apr 14, 2016
- TAU-METRIX, INC.
- Gary Steinbrueck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED PHOTODIODE FOR SEMICONDUCTOR SUBSTRATES
- Publication number 20130334644
- Publication date Dec 19, 2013
- TAU-METRIX, INC.
- Gary Steinbrueck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACTLESS TECHNIQUE FOR EVALUATING A FABRICATION OF A WAFER
- Publication number 20100304509
- Publication date Dec 2, 2010
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED PHOTODIODE FOR SEMICONDUCTOR SUBSTRATES
- Publication number 20100084729
- Publication date Apr 8, 2010
- Gary Steinbrueck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUE FOR EVALUATING A FABRICATION OF A DIE AND WAFER
- Publication number 20080315196
- Publication date Dec 25, 2008
- Majid AGHABABAZADEH
- G01 - MEASURING TESTING
Information Patent Application
INTRA-CHIP POWER AND TEST SIGNAL GENERATION FOR USE WITH TEST STRUC...
- Publication number 20080100319
- Publication date May 1, 2008
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND APPARATUS FOR USING TEST STRUCTURES INSIDE OF A CHIP DUR...
- Publication number 20070238206
- Publication date Oct 11, 2007
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND APPARATUS FOR USING TEST STRUCTURES INSIDE OF A CHIP DUR...
- Publication number 20070236232
- Publication date Oct 11, 2007
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Application
TECHNIQUE FOR EVALUATING A FABRICATION OF A DIE AND WAFER
- Publication number 20070187679
- Publication date Aug 16, 2007
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Application
TECHNIQUE FOR EVALUATING A FABRICATION OF A DIE AND WAFER
- Publication number 20070004063
- Publication date Jan 4, 2007
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Application
Intra-chip power and test signal generation for use with test struc...
- Publication number 20050090916
- Publication date Apr 28, 2005
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Application
System and apparatus for using test structures inside of a chip dur...
- Publication number 20050090027
- Publication date Apr 28, 2005
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Application
Technique for evaluating a fabrication of a die and wafer
- Publication number 20050085032
- Publication date Apr 21, 2005
- Majid Aghababazadeh
- G01 - MEASURING TESTING
Information Patent Application
Technique for evaluating a fabrication of a semiconductor component...
- Publication number 20050085932
- Publication date Apr 21, 2005
- Majid Aghababazadeh
- G01 - MEASURING TESTING

Majid Aghababazadeh

Person

Patents Grantslast 30 patents

Contactless technique for evaluating a fabrication of a wafer

Integrated photodiode for semiconductor substrates

Integrated photodiode for semiconductor substrates

Test structures for evaluating a fabrication of a die or a wafer

System and apparatus for using test structures inside of a chip dur...

Contactless technique for evaluating a fabrication of a wafer

System for using test structures to evaluate a fabrication of a wafer

Intra-chip power and test signal generation for use with test struc...

Technique for evaluating a fabrication of a die and wafer

Intra-clip power and test signal generation for use with test struc...

System and apparatus for using test structures inside of a chip dur...

Technique for evaluating a fabrication of a die and wafer

Patents Applicationslast 30 patents

INTEGRATED PHOTODIODE FOR SEMICONDUCTOR SUBSTRATES

INTEGRATED PHOTODIODE FOR SEMICONDUCTOR SUBSTRATES

CONTACTLESS TECHNIQUE FOR EVALUATING A FABRICATION OF A WAFER

INTEGRATED PHOTODIODE FOR SEMICONDUCTOR SUBSTRATES

TECHNIQUE FOR EVALUATING A FABRICATION OF A DIE AND WAFER

INTRA-CHIP POWER AND TEST SIGNAL GENERATION FOR USE WITH TEST STRUC...

SYSTEM AND APPARATUS FOR USING TEST STRUCTURES INSIDE OF A CHIP DUR...

SYSTEM AND APPARATUS FOR USING TEST STRUCTURES INSIDE OF A CHIP DUR...

TECHNIQUE FOR EVALUATING A FABRICATION OF A DIE AND WAFER

TECHNIQUE FOR EVALUATING A FABRICATION OF A DIE AND WAFER

Intra-chip power and test signal generation for use with test struc...

System and apparatus for using test structures inside of a chip dur...

Technique for evaluating a fabrication of a die and wafer

Technique for evaluating a fabrication of a semiconductor component...