Mamoru Kudo

Person

Kanagawa, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Phase error determination method and digital phase-locked loop system
- Patent number 7,730,366
- Issue date Jun 1, 2010
- Sony Corporation
- Shinobu Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device
- Patent number 7,578,676
- Issue date Aug 25, 2009
- Sony Corporation
- Shunichi Sukegawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device
- Patent number 7,554,186
- Issue date Jun 30, 2009
- Sony Corporation
- Mamoru Kudo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Phase error determination method and digital phase-locked loop system
- Patent number 7,469,367
- Issue date Dec 23, 2008
- Sony Corporation
- Shinobu Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device
- Patent number 7,351,068
- Issue date Apr 1, 2008
- Sony Corporation
- Shunichi Sukegawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Digital PLL device
- Patent number 7,342,986
- Issue date Mar 11, 2008
- Sony Corporation
- Shinobu Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase error determination method and digital phase-locked loop system
- Patent number 7,315,968
- Issue date Jan 1, 2008
- Sony Corporation
- Shinobu Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase-locked loop circuit for reproducing a channel clock
- Patent number 6,992,958
- Issue date Jan 31, 2006
- Sony Corporation
- Mamoru Kudo
- E05 - LOCKS KEYS WINDOW OR DOOR FITTINGS SAFES

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20080315386
- Publication date Dec 25, 2008
- SONY CORPORATION
- Mamoru Kudo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20080188096
- Publication date Aug 7, 2008
- SONY CORPORATION
- Shunichi SUKEGAWA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20070184677
- Publication date Aug 9, 2007
- SONY CORPORATION
- Shunichi SUKEGAWA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Phase error determination method and digital phase-locked loop system
- Publication number 20070094549
- Publication date Apr 26, 2007
- Sony Corporation
- Shinobu Nakamura
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Phase error determination method and digital phase-locked loop system
- Publication number 20070088992
- Publication date Apr 19, 2007
- Sony Corporation
- Shinobu Nakamura
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Recorder, recording method, reproducer, reproducing method, and rec...
- Publication number 20060098541
- Publication date May 11, 2006
- SONY CORPORATION
- Mamoru Kudo
- G11 - INFORMATION STORAGE
Information Patent Application
Phase error determination method and digital phase-locked loop system
- Publication number 20050022076
- Publication date Jan 27, 2005
- Shinobu Nakamura
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Digital PLL device
- Publication number 20040264623
- Publication date Dec 30, 2004
- Shinobu Nakamura
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Phase-locked loop circuit
- Publication number 20020105365
- Publication date Aug 8, 2002
- Mamoru Kudo
- E05 - LOCKS KEYS WINDOW OR DOOR FITTINGS SAFES

Mamoru Kudo

Person

Patents Grantslast 30 patents

Phase error determination method and digital phase-locked loop system

Semiconductor device

Semiconductor device

Phase error determination method and digital phase-locked loop system

Semiconductor device

Digital PLL device

Phase error determination method and digital phase-locked loop system

Phase-locked loop circuit for reproducing a channel clock

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE

Phase error determination method and digital phase-locked loop system

Phase error determination method and digital phase-locked loop system

Recorder, recording method, reproducer, reproducing method, and rec...

Phase error determination method and digital phase-locked loop system

Digital PLL device

Phase-locked loop circuit