Mamun Rashid

Person

Fairfield, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Even and odd frame combination data path architecture
- Patent number 8,225,016
- Issue date Jul 17, 2012
- Intel Corporation
- Mamun Ur Rashid
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Nibble de-skew method, apparatus, and system
- Patent number 7,954,001
- Issue date May 31, 2011
- Intel Corporation
- Aaron K. Martin
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock synchronization scheme for deskewing operations in a data int...
- Patent number 7,805,627
- Issue date Sep 28, 2010
- Intel Corporation
- Mamun Ur Rashid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock deskewing method, apparatus, and system
- Patent number 7,668,524
- Issue date Feb 23, 2010
- Intel Corporation
- Hon-Mo Raymond Law
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimizing clock crossing and data path latency
- Patent number 7,590,789
- Issue date Sep 15, 2009
- Intel Corporation
- Mamun Ur Rashid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clocking architecture using a bidirectional clock port
- Patent number 7,555,670
- Issue date Jun 30, 2009
- Intel Corporation
- Ravindran Mohanavelu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Receive clock deskewing method, apparatus, and system
- Patent number 7,439,788
- Issue date Oct 21, 2008
- Intel Corporation
- Hon-Mo Raymond Law
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Nibble de-skew method, apparatus, and system
- Patent number 7,401,246
- Issue date Jul 15, 2008
- Intel Corporation
- Aaron K. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modular memory controller clocking architecture
- Patent number 7,388,795
- Issue date Jun 17, 2008
- Intel Corporation
- Hing To
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Latency normalization by balancing early and late clocks
- Patent number 7,324,403
- Issue date Jan 29, 2008
- Intel Corporation
- Hing Yan To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Closed-loop delay compensation for driver
- Patent number 7,230,464
- Issue date Jun 12, 2007
- Intel Corporation
- Mamun Ur Rashid
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Closed-loop control of driver slew rate
- Patent number 7,109,768
- Issue date Sep 19, 2006
- Intel Corporation
- Mamun Ur Rashid
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Test circuit for delay lock loops
- Patent number 7,061,224
- Issue date Jun 13, 2006
- Intel Corporation
- Akira Kakizawa
- G01 - MEASURING TESTING
Information Patent Grant
Programmable direct interpolating delay locked loop
- Patent number 6,958,634
- Issue date Oct 25, 2005
- Intel Corporation
- Mamun Ur Rashid
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Special test modes for a page buffer shared resource in a memory de...
- Patent number 5,835,927
- Issue date Nov 10, 1998
- Intel Corporation
- Mickey L. Fandrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and circuitry for usage of partially functional nonvolatile...
- Patent number 5,822,256
- Issue date Oct 13, 1998
- Intel Corporation
- Mark E. Bauer
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for allocating and sharingpage buffers for a flas...
- Patent number 5,802,552
- Issue date Sep 1, 1998
- Intel Corporation
- Mickey L. Fandrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Special test modes for a page buffer shared resource in a memory de...
- Patent number 5,623,620
- Issue date Apr 22, 1997
- Intel Corporation
- Mickey L. Fandrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronous address latching for memory arrays
- Patent number 5,586,081
- Issue date Dec 17, 1996
- Intel Corporation
- Duane R. Mills
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for verifying the programming of multi-level f...
- Patent number 5,523,972
- Issue date Jun 4, 1996
- Intel Corporation
- Mamun Rashid
- G11 - INFORMATION STORAGE
Information Patent Grant
Synchronous address latching for memory arrays
- Patent number 5,497,355
- Issue date Mar 5, 1996
- Intel Corporation
- Duane R. Mills
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
External tester control for flash memory
- Patent number 5,410,544
- Issue date Apr 25, 1995
- Intel Corporation
- Jerry A. Kreifels
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Even and odd frame combination data path architecture
- Publication number 20090172215
- Publication date Jul 2, 2009
- Mamun Ur Rashid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimizing clock crossing and data path latency
- Publication number 20090150586
- Publication date Jun 11, 2009
- Mamun Ur Rashid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock synchronization scheme for deskewing operations in a data int...
- Publication number 20080244298
- Publication date Oct 2, 2008
- Mamun Ur Rashid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NIBBLE DE-SKEW METHOD, APPARATUS, AND SYSTEM
- Publication number 20080244303
- Publication date Oct 2, 2008
- Aaron K. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODULAR MEMORY CONTROLLER CLOCKING ARCHITECTURE
- Publication number 20080162977
- Publication date Jul 3, 2008
- Hing To
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock deskewing method, apparatus, and system
- Publication number 20070149142
- Publication date Jun 28, 2007
- Intel Corporation
- Hon-Mo Raymond Law
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Receive clock deskewing method, apparatus, and system
- Publication number 20070146035
- Publication date Jun 28, 2007
- Intel Corporation
- Hon-Mo Raymond Law
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Clocking architecture using a bi-directional reference clock
- Publication number 20070091712
- Publication date Apr 26, 2007
- Intel Corporation
- Ravindran Mohanavelu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to perform clock crossing on data paths
- Publication number 20070067594
- Publication date Mar 22, 2007
- Mamun U. Rashid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Nibble de-skew method, apparatus, and system
- Publication number 20070006011
- Publication date Jan 4, 2007
- Intel Corporation
- Aaron K. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latency normalization by balancing early and late clocks
- Publication number 20060067155
- Publication date Mar 30, 2006
- Hing Yan To
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Test circuit for delay lock loops
- Publication number 20060066291
- Publication date Mar 30, 2006
- Intel Corporation
- Akira Kakizawa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Closed-loop delay compensation for driver
- Publication number 20050285642
- Publication date Dec 29, 2005
- Mamun Ur Rashid
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Closed-loop control of driver slew rate
- Publication number 20050285646
- Publication date Dec 29, 2005
- Mamun Ur Rashid
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable direct interpolating delay locked loop
- Publication number 20050140416
- Publication date Jun 30, 2005
- Mamun Ur Rashid
- H03 - BASIC ELECTRONIC CIRCUITRY

Mamun Rashid

Person

Patents Grantslast 30 patents

Even and odd frame combination data path architecture

Nibble de-skew method, apparatus, and system

Clock synchronization scheme for deskewing operations in a data int...

Clock deskewing method, apparatus, and system

Optimizing clock crossing and data path latency

Clocking architecture using a bidirectional clock port

Receive clock deskewing method, apparatus, and system

Nibble de-skew method, apparatus, and system

Modular memory controller clocking architecture

Latency normalization by balancing early and late clocks

Closed-loop delay compensation for driver

Closed-loop control of driver slew rate

Test circuit for delay lock loops

Programmable direct interpolating delay locked loop

Special test modes for a page buffer shared resource in a memory de...

Method and circuitry for usage of partially functional nonvolatile...

System and method for allocating and sharingpage buffers for a flas...

Special test modes for a page buffer shared resource in a memory de...

Synchronous address latching for memory arrays

Method and apparatus for verifying the programming of multi-level f...

Synchronous address latching for memory arrays

External tester control for flash memory

Patents Applicationslast 30 patents

Even and odd frame combination data path architecture

Optimizing clock crossing and data path latency

Clock synchronization scheme for deskewing operations in a data int...

NIBBLE DE-SKEW METHOD, APPARATUS, AND SYSTEM

MODULAR MEMORY CONTROLLER CLOCKING ARCHITECTURE

Clock deskewing method, apparatus, and system

Receive clock deskewing method, apparatus, and system

Clocking architecture using a bi-directional reference clock

Method and apparatus to perform clock crossing on data paths

Nibble de-skew method, apparatus, and system

Latency normalization by balancing early and late clocks

Test circuit for delay lock loops

Closed-loop delay compensation for driver

Closed-loop control of driver slew rate

Programmable direct interpolating delay locked loop