Man Fai Ng

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device fabrication method for improved isolation regi...
- Patent number 8,987,110
- Issue date Mar 24, 2015
- GLOBALFOUNDRIES, INC.
- Man Fai Ng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal gate fill by optimizing etch in sacrificial gate profile
- Patent number 8,765,537
- Issue date Jul 1, 2014
- GLOBALFOUNDRIES Inc.
- Man Fai Ng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming barrier regions within regions of insulating ma...
- Patent number 8,680,624
- Issue date Mar 25, 2014
- GLOBALFOUNDRIES, INC.
- Man Fai Ng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices having stressor regions and related fabricati...
- Patent number 8,674,438
- Issue date Mar 18, 2014
- GLOBALFOUNDRIES, INC.
- Bin Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ETSOI with reduced extension resistance
- Patent number 8,518,758
- Issue date Aug 27, 2013
- GLOBALFOUNDRIES Inc.
- Bin Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Short channel semiconductor devices with reduced halo diffusion
- Patent number 8,445,342
- Issue date May 21, 2013
- GLOBALFOUNDRIES Inc.
- Bin Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices having stressor regions and related fabricati...
- Patent number 8,394,691
- Issue date Mar 12, 2013
- GLOBALFOUNDRIES, INC.
- Bin Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate etch optimization through silicon dopant profile change
- Patent number 8,390,042
- Issue date Mar 5, 2013
- GLOBALFOUNDRIES Inc.
- Man Fai Ng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
eFUSE enablement with thin polysilicon or amorphous-silicon gate-st...
- Patent number 8,329,515
- Issue date Dec 11, 2012
- GLOBALFOUNDRIES Inc.
- Bin Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming barrier regions within regions of insulating ma...
- Patent number 8,222,093
- Issue date Jul 17, 2012
- GLOBALFOUNDRIES, INC.
- Man Fai Ng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device fabrication method for improved isolation regi...
- Patent number 8,198,170
- Issue date Jun 12, 2012
- GLOBALFOUNDRIES, INC.
- Man Fai Ng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate etch optimization through silicon dopant profile change
- Patent number 8,124,515
- Issue date Feb 28, 2012
- GLOBALFOUNDRIES Inc.
- Man Fai Ng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for protecting gate stacks during fabrication of semiconduc...
- Patent number 8,084,828
- Issue date Dec 27, 2011
- GLOBALFOUNDRIES Inc.
- Rohit Pal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for protecting gate stacks during fabrication of semiconduc...
- Patent number 7,763,508
- Issue date Jul 27, 2010
- GLOBALFOUNDRIES Inc.
- Rohit Pal
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
ETSOI WITH REDUCED EXTENSION RESISTANCE
- Publication number 20160260841
- Publication date Sep 8, 2016
- GLOBALFOUNDRIES INC.
- Bin YANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF MANUFACTURING INTEGRATED CIRCUITS HAVING A COMPRESSIVE N...
- Publication number 20140183720
- Publication date Jul 3, 2014
- International Business Machines Corporation
- Scott Beasor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETSOI WITH REDUCED EXTENSION RESISTANCE
- Publication number 20130320447
- Publication date Dec 5, 2013
- GLOBALFOUNDERIES Inc.
- Bin YANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHORT CHANNEL SEMICONDUCTOR DEVICES WITH REDUCED HALO DIFFUSION
- Publication number 20130249000
- Publication date Sep 26, 2013
- GLOBALFOUNDRIES INC.
- Bin Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATI...
- Publication number 20130153927
- Publication date Jun 20, 2013
- GLOBALFOUNDRIES, Inc.
- Bin Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL GATE FILL BY OPTIMIZING ETCH IN SACRIFICIAL GATE PROFILE
- Publication number 20130005128
- Publication date Jan 3, 2013
- GLOBALFOUNDRIES INC.
- Man Fai Ng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FORMING BARRIER REGIONS WITHIN REGIONS OF INSULATING MA...
- Publication number 20120235237
- Publication date Sep 20, 2012
- GLOBALFOUNDRIES INC.
- Man Fai Ng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE FABRICATION METHOD FOR IMPROVED ISOLATION REGI...
- Publication number 20120220095
- Publication date Aug 30, 2012
- GLOBALFOUNDRIES INC.
- Man Fai Ng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE ETCH OPTIMIZATION THROUGH SILICON DOPANT PROFILE CHANGE
- Publication number 20120119308
- Publication date May 17, 2012
- GLOBALFOUNDRIES INC.
- Man Fai Ng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE FABRICATION METHOD FOR IMPROVED ISOLATION REGI...
- Publication number 20120094466
- Publication date Apr 19, 2012
- Man Fai NG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHORT CHANNEL SEMICONDUCTOR DEVICES WITH REDUCED HALO DIFFUSION
- Publication number 20110316093
- Publication date Dec 29, 2011
- GLOBALFOUNDRIES INC.
- Bin Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATI...
- Publication number 20110303954
- Publication date Dec 15, 2011
- GLOBALFOUNDRIES INC.
- Bin Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL GATE FILL BY OPTIMIZING ETCH IN SACRIFICIAL GATE PROFILE
- Publication number 20110241118
- Publication date Oct 6, 2011
- GLOBALFOUNDRIES INC.
- Man Fai Ng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETSOI WITH REDUCED EXTENSION RESISTANCE
- Publication number 20110227157
- Publication date Sep 22, 2011
- GLOBALFOUNDRIES INC.
- Bin Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FORMING BARRIER REGIONS WITHIN REGIONS OF INSULATING MA...
- Publication number 20110198694
- Publication date Aug 18, 2011
- GLOBALFOUNDRIES INC.
- Man Fai Ng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
eFUSE ENABLEMENT WITH THIN POLYSILICON OR AMORPHOUS-SILICON GATE-ST...
- Publication number 20110156146
- Publication date Jun 30, 2011
- GLOBALFOUNDRIES INC.
- Bin Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE ETCH OPTIMIZATION THROUGH SILICON DOPANT PROFILE CHANGE
- Publication number 20100295103
- Publication date Nov 25, 2010
- GLOBALFOUNDRIES INC.
- Man Fai Ng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUC...
- Publication number 20100244156
- Publication date Sep 30, 2010
- GLOBALFOUNDRIES INC.
- Rohit Pal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUC...
- Publication number 20100109056
- Publication date May 6, 2010
- Advanced Micro Devices, Inc.
- Rohit PAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH IMPROVED CONTACT PLUGS, AND RELATED FABRI...
- Publication number 20100072623
- Publication date Mar 25, 2010
- Advanced Micro Devices, Inc.
- Christopher M. PRINDLE
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Semiconductor device fabrication method for improved isolation regi...

Metal gate fill by optimizing etch in sacrificial gate profile

Methods for forming barrier regions within regions of insulating ma...

Semiconductor devices having stressor regions and related fabricati...

ETSOI with reduced extension resistance

Short channel semiconductor devices with reduced halo diffusion

Semiconductor devices having stressor regions and related fabricati...

Gate etch optimization through silicon dopant profile change

eFUSE enablement with thin polysilicon or amorphous-silicon gate-st...

Methods for forming barrier regions within regions of insulating ma...

Semiconductor device fabrication method for improved isolation regi...

Gate etch optimization through silicon dopant profile change

Methods for protecting gate stacks during fabrication of semiconduc...

Methods for protecting gate stacks during fabrication of semiconduc...

Patents Applicationslast 30 patents

ETSOI WITH REDUCED EXTENSION RESISTANCE

METHODS OF MANUFACTURING INTEGRATED CIRCUITS HAVING A COMPRESSIVE N...

ETSOI WITH REDUCED EXTENSION RESISTANCE

SHORT CHANNEL SEMICONDUCTOR DEVICES WITH REDUCED HALO DIFFUSION

SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATI...

METAL GATE FILL BY OPTIMIZING ETCH IN SACRIFICIAL GATE PROFILE

METHODS FOR FORMING BARRIER REGIONS WITHIN REGIONS OF INSULATING MA...

SEMICONDUCTOR DEVICE FABRICATION METHOD FOR IMPROVED ISOLATION REGI...

GATE ETCH OPTIMIZATION THROUGH SILICON DOPANT PROFILE CHANGE

SEMICONDUCTOR DEVICE FABRICATION METHOD FOR IMPROVED ISOLATION REGI...

SHORT CHANNEL SEMICONDUCTOR DEVICES WITH REDUCED HALO DIFFUSION

SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATI...

METAL GATE FILL BY OPTIMIZING ETCH IN SACRIFICIAL GATE PROFILE

ETSOI WITH REDUCED EXTENSION RESISTANCE

METHODS FOR FORMING BARRIER REGIONS WITHIN REGIONS OF INSULATING MA...

eFUSE ENABLEMENT WITH THIN POLYSILICON OR AMORPHOUS-SILICON GATE-ST...

GATE ETCH OPTIMIZATION THROUGH SILICON DOPANT PROFILE CHANGE

METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUC...

METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUC...

SEMICONDUCTOR DEVICE WITH IMPROVED CONTACT PLUGS, AND RELATED FABRI...