Manas Mandal

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Techniques for configuring a processor to function as multiple, sep...
- Patent number 11,893,423
- Issue date Feb 6, 2024
- NVIDIA Corporation
- Jerome F. Duluk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for configuring a processor to function as multiple, sep...
- Patent number 11,663,036
- Issue date May 30, 2023
- NVIDIA Corporation
- Jerome F. Duluk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for configuring a processor to function as multiple, sep...
- Patent number 11,635,986
- Issue date Apr 25, 2023
- NVIDIA Corporation
- Jerome F. Duluk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for reconfiguring partitions in a parallel processing sy...
- Patent number 11,579,925
- Issue date Feb 14, 2023
- NVIDIA Corporation
- Jerome F. Duluk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for configuring a processor to function as multiple, sep...
- Patent number 11,249,905
- Issue date Feb 15, 2022
- NVIDIA Corporation
- Jerome F. Duluk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Raster operations unit with interleaving of read and write requests...
- Patent number 8,035,647
- Issue date Oct 11, 2011
- NVIDIA Corporation
- Donald A. Bittel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packet combiner for a packetized bus with dynamic holdoff time
- Patent number 7,526,593
- Issue date Apr 28, 2009
- NVIDIA Corporation
- Manas Mandal
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TECHNIQUES FOR MEMORY ERROR ISOLATION
- Publication number 20210294707
- Publication date Sep 23, 2021
- NVIDIA Corporation
- Jonathon Stuart Ramsay Evans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR CONFIGURING A PROCESSOR TO FUNCTION AS MULTIPLE, SEP...
- Publication number 20210157651
- Publication date May 27, 2021
- NVIDIA Corporation
- Jerome F. DULUK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR CONFIGURING A PROCESSOR TO FUNCTION AS MULTIPLE, SEP...
- Publication number 20210073042
- Publication date Mar 11, 2021
- NVIDIA Corporation
- Jerome F. DULUK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR CONFIGURING A PROCESSOR TO FUNCTION AS MULTIPLE, SEP...
- Publication number 20210073125
- Publication date Mar 11, 2021
- NVIDIA Corporation
- Jerome F. DULUK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR CONFIGURING A PROCESSOR TO FUNCTION AS MULTIPLE, SEP...
- Publication number 20210073035
- Publication date Mar 11, 2021
- NVIDIA Corporation
- Jerome F. DULUK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR CONFIGURING A PROCESSOR TO FUNCTION AS MULTIPLE, SEP...
- Publication number 20210073025
- Publication date Mar 11, 2021
- NVIDIA Corporation
- Jerome F. DULUK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INLINE ERROR DETECTION AND CORRECTION TECHNIQUES
- Publication number 20180121287
- Publication date May 3, 2018
- NVIDIA Corporation
- Michael Wasserman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Packet Combiner for a Packetized Bus with Dynamic Holdoff time
- Publication number 20070079044
- Publication date Apr 5, 2007
- NVIDIA Corporation
- Manas Mandal
- G06 - COMPUTING CALCULATING COUNTING

Manas Mandal

Person

Patents Grantslast 30 patents

Techniques for configuring a processor to function as multiple, sep...

Techniques for configuring a processor to function as multiple, sep...

Techniques for configuring a processor to function as multiple, sep...

Techniques for reconfiguring partitions in a parallel processing sy...

Techniques for configuring a processor to function as multiple, sep...

Raster operations unit with interleaving of read and write requests...

Packet combiner for a packetized bus with dynamic holdoff time

Patents Applicationslast 30 patents

TECHNIQUES FOR MEMORY ERROR ISOLATION

TECHNIQUES FOR CONFIGURING A PROCESSOR TO FUNCTION AS MULTIPLE, SEP...

TECHNIQUES FOR CONFIGURING A PROCESSOR TO FUNCTION AS MULTIPLE, SEP...

TECHNIQUES FOR CONFIGURING A PROCESSOR TO FUNCTION AS MULTIPLE, SEP...

TECHNIQUES FOR CONFIGURING A PROCESSOR TO FUNCTION AS MULTIPLE, SEP...

TECHNIQUES FOR CONFIGURING A PROCESSOR TO FUNCTION AS MULTIPLE, SEP...

INLINE ERROR DETECTION AND CORRECTION TECHNIQUES

Packet Combiner for a Packetized Bus with Dynamic Holdoff time