Manish Bhatia

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Delhi, IN

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Patents Grantslast 30 patents

Information Patent Grant
Method for compaction of timing exception paths
- Patent number 8,042,085
- Issue date Oct 18, 2011
- Atrenta, Inc.
- Solaiman Rahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pattern recognition in an integrated circuit design
- Patent number 7,216,321
- Issue date May 8, 2007
- Atrenta, Inc.
- Bernard Murphy
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR COMPACTION OF TIMING EXCEPTION PATHS
- Publication number 20100064263
- Publication date Mar 11, 2010
- ATRENTA, INC.
- Solaiman Rahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pattern recognition in an integrated circuit design
- Publication number 20050108675
- Publication date May 19, 2005
- ATRENTA, INC.
- Bernard Murphy
- G06 - COMPUTING CALCULATING COUNTING