Manish Pandey

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Estimating hardness of formal properties using on-the-fly machine l...
- Patent number 11,501,048
- Issue date Nov 15, 2022
- Synopsys, Inc.
- Arunava Saha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RTL verification using computational complexity-based property rank...
- Patent number 10,521,536
- Issue date Dec 31, 2019
- Synopsys, Inc.
- Jinqing Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Formal verification using cached search path information to verify...
- Patent number 10,503,853
- Issue date Dec 10, 2019
- Synopsys, Inc.
- Arunava Saha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing model checks of sequential designs
- Patent number 10,140,403
- Issue date Nov 27, 2018
- Synopsys Inc.
- Jinqing Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing model checks of sequential designs
- Patent number 9,430,595
- Issue date Aug 30, 2016
- Synopsys, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for generating design constraints
- Patent number 8,627,249
- Issue date Jan 7, 2014
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for implementing electronic designs having pow...
- Patent number RE44479
- Issue date Sep 3, 2013
- Cadence Design Systems, Inc.
- Qi Wang
- 716 - Computer-aided design and analysis of circuits and semiconductor masks
Information Patent Grant
Method and mechanism for implementing electronic designs having pow...
- Patent number 8,516,422
- Issue date Aug 20, 2013
- Cadence Design Systems, Inc.
- Qi Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying multiple constraints for circuit designs
- Patent number 8,209,648
- Issue date Jun 26, 2012
- Cadence Design Systems, Inc.
- Shan-Chyun Ku
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for generating design constraints
- Patent number 7,962,886
- Issue date Jun 14, 2011
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for implementing electronic designs having pow...
- Patent number 7,739,629
- Issue date Jun 15, 2010
- Cadence Design Systems, Inc.
- Qi Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for verifying power specifications of a low power...
- Patent number 7,694,251
- Issue date Apr 6, 2010
- Cadence Design Systems, Inc.
- Bharat Chandramouli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for equivalence checking of a low power design
- Patent number 7,669,165
- Issue date Feb 23, 2010
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for analyzing circuits having MOS devices
- Patent number 7,644,380
- Issue date Jan 5, 2010
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for logic equivalence checking
- Patent number 7,620,919
- Issue date Nov 17, 2009
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for logic equivalence checking
- Patent number 7,620,918
- Issue date Nov 17, 2009
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for global coverage analysis
- Patent number 7,587,690
- Issue date Sep 8, 2009
- Cadence Design Systems, Inc.
- Bret Siarkowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for logic equivalence checking
- Patent number 7,266,790
- Issue date Sep 4, 2007
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for verification of memories at multiple abstr...
- Patent number 6,848,084
- Issue date Jan 25, 2005
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
RTL Verification Using Computational Complexity-Based Property Rank...
- Publication number 20180144071
- Publication date May 24, 2018
- Synopsys, Inc.
- Jinqing Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING MODEL CHECKS OF SEQUENTIAL DESIGNS
- Publication number 20160125111
- Publication date May 5, 2016
- Synopsys Inc.
- Jinqing Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING MODEL CHECKS OF SEQUENTIAL DESIGNS
- Publication number 20140157216
- Publication date Jun 5, 2014
- Synopsys Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Establishing a Secure Channel between a Server and a Portable Device
- Publication number 20100250796
- Publication date Sep 30, 2010
- David Jevans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR GLOBAL COVERAGE ANALYSIS
- Publication number 20090064071
- Publication date Mar 5, 2009
- Cadence Design Systems, Inc.
- Bret SIARKOWSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for equivalence checking of a low power design
- Publication number 20080127014
- Publication date May 29, 2008
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for verifying power specifications of a low power...
- Publication number 20080127015
- Publication date May 29, 2008
- Bharat Chandramouli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Logic Equivalence Checking
- Publication number 20070294650
- Publication date Dec 20, 2007
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Logic Equivalence Checking
- Publication number 20070294649
- Publication date Dec 20, 2007
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and mechanism for implementing electronic designs having pow...
- Publication number 20070245285
- Publication date Oct 18, 2007
- Qi Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for logic equivalence checking
- Publication number 20040177332
- Publication date Sep 9, 2004
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING

Manish Pandey

Person

Patents Grantslast 30 patents

Estimating hardness of formal properties using on-the-fly machine l...

RTL verification using computational complexity-based property rank...

Formal verification using cached search path information to verify...

Managing model checks of sequential designs

Managing model checks of sequential designs

Method and system for generating design constraints

Method and mechanism for implementing electronic designs having pow...

Method and mechanism for implementing electronic designs having pow...

Verifying multiple constraints for circuit designs

Method and system for generating design constraints

Method and mechanism for implementing electronic designs having pow...

Method and system for verifying power specifications of a low power...

Method and system for equivalence checking of a low power design

Method for analyzing circuits having MOS devices

Method and system for logic equivalence checking

Method and system for logic equivalence checking

Method and system for global coverage analysis

Method and system for logic equivalence checking

Method and apparatus for verification of memories at multiple abstr...

Patents Applicationslast 30 patents

RTL Verification Using Computational Complexity-Based Property Rank...

MANAGING MODEL CHECKS OF SEQUENTIAL DESIGNS

MANAGING MODEL CHECKS OF SEQUENTIAL DESIGNS

Establishing a Secure Channel between a Server and a Portable Device

METHOD AND SYSTEM FOR GLOBAL COVERAGE ANALYSIS

Method and system for equivalence checking of a low power design

Method and system for verifying power specifications of a low power...

Method and System for Logic Equivalence Checking

Method and System for Logic Equivalence Checking

Method and mechanism for implementing electronic designs having pow...

Method and system for logic equivalence checking