Manoj Dusanapudi

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Performance and reliability of processor store operation data trans...
- Patent number 12,141,071
- Issue date Nov 12, 2024
- International Business Machnes Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Validation of store coherence relative to page translation invalida...
- Patent number 12,130,749
- Issue date Oct 29, 2024
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence validation using delayed fulfillment of L2 requests
- Patent number 12,118,355
- Issue date Oct 15, 2024
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Validation of store coherence relative to page translation invalida...
- Patent number 11,620,235
- Issue date Apr 4, 2023
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test case generation for a hardware state space
- Patent number 11,163,661
- Issue date Nov 2, 2021
- International Business Machines Corporation
- Madhusudan Kadiyala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
List insertion in test segments with non-naturally aligned data bou...
- Patent number 11,094,391
- Issue date Aug 17, 2021
- International Business Machines Corporation
- Manoj Dusanapudi
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, system, and apparatus for stress testing memory translation...
- Patent number 11,061,821
- Issue date Jul 13, 2021
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling segment layout in a stress test for a processor memory...
- Patent number 10,877,864
- Issue date Dec 29, 2020
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core pairing in multicore systems
- Patent number 10,831,620
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for testing processor errors
- Patent number 10,748,637
- Issue date Aug 18, 2020
- International Business Machines Corporation
- Nelson Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficiently generating effective address translations for memory ma...
- Patent number 10,713,179
- Issue date Jul 14, 2020
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stress testing a processor memory with a link stack
- Patent number 10,540,249
- Issue date Jan 21, 2020
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and apparatus for stress testing memory translation...
- Patent number 10,521,355
- Issue date Dec 31, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient testing of direct memory address translation
- Patent number 10,489,261
- Issue date Nov 26, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Replicating test case data into a cache with non-naturally aligned...
- Patent number 10,489,259
- Issue date Nov 26, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient testing of direct memory address translation
- Patent number 10,481,991
- Issue date Nov 19, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
List insertion in test segments with non-naturally aligned data bou...
- Patent number 10,438,682
- Issue date Oct 8, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G11 - INFORMATION STORAGE
Information Patent Grant
Efficiently generating effective address translations for memory ma...
- Patent number 10,346,314
- Issue date Jul 9, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test case generation
- Patent number 10,318,667
- Issue date Jun 11, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Validation of correctness of interrupt triggers and delivery
- Patent number 10,318,456
- Issue date Jun 11, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stress testing a processor memory with a link stack
- Patent number 10,261,878
- Issue date Apr 16, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying stale entries in address translation cache
- Patent number 10,261,917
- Issue date Apr 16, 2019
- International Business Machines Corporation
- Vinod Bussa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient validation/verification of coherency and snoop filtering...
- Patent number 10,241,880
- Issue date Mar 26, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing speculative instruction execution with test cases placed in...
- Patent number 10,223,225
- Issue date Mar 5, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient validation of transactional memory in a computer processor
- Patent number 10,169,181
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Vinod Bussa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient testing of direct memory address translation
- Patent number 10,169,185
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Replicating test code and test data into a cache with non-naturally...
- Patent number 10,169,180
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient testing of direct memory address translation
- Patent number 10,169,186
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Replicating test case data into a cache and cache inhibited memory
- Patent number 10,055,320
- Issue date Aug 21, 2018
- International Business Machines Corporation
- Manoj Dusanapudi
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing a non-core MMU
- Patent number 10,007,568
- Issue date Jun 26, 2018
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PERFORMANCE AND RELIABILITY OF PROCESSOR STORE OPERATION DATA TRANS...
- Publication number 20240028518
- Publication date Jan 25, 2024
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HAZARD GENERATING FOR SPECULATIVE CORES IN A MICROPROCESSOR
- Publication number 20230195981
- Publication date Jun 22, 2023
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VALIDATION OF STORE COHERENCE RELATIVE TO PAGE TRANSLATION INVALIDA...
- Publication number 20230195649
- Publication date Jun 22, 2023
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE COHERENCE VALIDATION USING DELAYED FULFILLMENT OF L2 REQUESTS
- Publication number 20230122466
- Publication date Apr 20, 2023
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VALIDATION OF STORE COHERENCE RELATIVE TO PAGE TRANSLATION INVALIDA...
- Publication number 20230105945
- Publication date Apr 6, 2023
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST CASE GENERATION FOR A HARDWARE STATE SPACE
- Publication number 20210042202
- Publication date Feb 11, 2021
- International Business Machines Corporation
- MADHUSUDAN KADIYALA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLING SEGMENT LAYOUT IN A STRESS TEST FOR A PROCESSOR MEMORY...
- Publication number 20200201728
- Publication date Jun 25, 2020
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR STRESS TESTING MEMORY TRANSLATION...
- Publication number 20200089621
- Publication date Mar 19, 2020
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Testing Processor Errors
- Publication number 20200035319
- Publication date Jan 30, 2020
- International Business Machines Corporation
- Nelson Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LIST INSERTION IN TEST SEGMENTS WITH NON-NATURALLY ALIGNED DATA BOU...
- Publication number 20190287639
- Publication date Sep 19, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G11 - INFORMATION STORAGE
Information Patent Application
EFFICIENTLY GENERATING EFFECTIVE ADDRESS TRANSLATIONS FOR MEMORY MA...
- Publication number 20190227945
- Publication date Jul 25, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LIST INSERTION IN TEST SEGMENTS WITH NON-NATURALLY ALIGNED DATA BOU...
- Publication number 20190198132
- Publication date Jun 27, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR STRESS TESTING MEMORY TRANSLATION...
- Publication number 20190188146
- Publication date Jun 20, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VALIDATION OF CORRECTNESS OF INTERRUPT TRIGGERS AND DELIVERY
- Publication number 20190138472
- Publication date May 9, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT TESTING OF DIRECT MEMORY ADDRESS TRANSLATION
- Publication number 20190050314
- Publication date Feb 14, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT TESTING OF DIRECT MEMORY ADDRESS TRANSLATION
- Publication number 20190050315
- Publication date Feb 14, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRESS TESTING A PROCESSOR MEMORY WITH A LINK STACK
- Publication number 20180267875
- Publication date Sep 20, 2018
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRESS TESTING A PROCESSOR MEMORY WITH A LINK STACK
- Publication number 20180267876
- Publication date Sep 20, 2018
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REPLICATING TEST CASE DATA INTO A CACHE WITH NON-NATURALLY ALIGNED...
- Publication number 20180157567
- Publication date Jun 7, 2018
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING SPECULATIVE INSTRUCTION EXECUTION WITH TEST CASES PLACED IN...
- Publication number 20180129577
- Publication date May 10, 2018
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IDENTIFYING STALE ENTRIES IN ADDRESS TRANSLATION CACHE
- Publication number 20180121365
- Publication date May 3, 2018
- International Business Machines Corporation
- Vinod Bussa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT VALIDATION OF TRANSACTIONAL MEMORY IN A COMPUTER PROCESSOR
- Publication number 20180074926
- Publication date Mar 15, 2018
- International Business Machines Corporation
- Vinod Bussa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENTLY GENERATING EFFECTIVE ADDRESS TRANSLATIONS FOR MEMORY MA...
- Publication number 20180039579
- Publication date Feb 8, 2018
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REPLICATING TEST CASE DATA INTO A CACHE AND CACHE INHIBITED MEMORY
- Publication number 20180019021
- Publication date Jan 18, 2018
- International Business Machines Corporation
- Manoj Dusanapudi
- G11 - INFORMATION STORAGE
Information Patent Application
CORE PAIRING IN MULTICORE SYSTEMS
- Publication number 20170364421
- Publication date Dec 21, 2017
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONIZATION OF HARDWARE AGENTS IN A COMPUTER SYSTEM
- Publication number 20170344466
- Publication date Nov 30, 2017
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REPLICATING TEST CODE AND TEST DATA INTO A CACHE WITH NON-NATURALLY...
- Publication number 20170329688
- Publication date Nov 16, 2017
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT VALIDATION/VERIFICATION OF COHERENCY AND SNOOP FILTERING...
- Publication number 20170220440
- Publication date Aug 3, 2017
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REPLICATING TEST CASE DATA INTO A CACHE WITH NON-NATURALLY ALIGNED...
- Publication number 20170220442
- Publication date Aug 3, 2017
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REPLICATING TEST CASE DATA INTO A CACHE WITH NON-NATURALLY ALIGNED...
- Publication number 20170220438
- Publication date Aug 3, 2017
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING

Manoj Dusanapudi

Person

Patents Grantslast 30 patents

Performance and reliability of processor store operation data trans...

Validation of store coherence relative to page translation invalida...

Cache coherence validation using delayed fulfillment of L2 requests

Validation of store coherence relative to page translation invalida...

Test case generation for a hardware state space

List insertion in test segments with non-naturally aligned data bou...

Method, system, and apparatus for stress testing memory translation...

Controlling segment layout in a stress test for a processor memory...

Core pairing in multicore systems

System and method for testing processor errors

Efficiently generating effective address translations for memory ma...

Stress testing a processor memory with a link stack

Method, system, and apparatus for stress testing memory translation...

Efficient testing of direct memory address translation

Replicating test case data into a cache with non-naturally aligned...

Efficient testing of direct memory address translation

List insertion in test segments with non-naturally aligned data bou...

Efficiently generating effective address translations for memory ma...

Test case generation

Validation of correctness of interrupt triggers and delivery

Stress testing a processor memory with a link stack

Identifying stale entries in address translation cache

Efficient validation/verification of coherency and snoop filtering...

Testing speculative instruction execution with test cases placed in...

Efficient validation of transactional memory in a computer processor

Efficient testing of direct memory address translation

Replicating test code and test data into a cache with non-naturally...

Efficient testing of direct memory address translation

Replicating test case data into a cache and cache inhibited memory

Testing a non-core MMU

Patents Applicationslast 30 patents

PERFORMANCE AND RELIABILITY OF PROCESSOR STORE OPERATION DATA TRANS...

HAZARD GENERATING FOR SPECULATIVE CORES IN A MICROPROCESSOR

VALIDATION OF STORE COHERENCE RELATIVE TO PAGE TRANSLATION INVALIDA...

CACHE COHERENCE VALIDATION USING DELAYED FULFILLMENT OF L2 REQUESTS

VALIDATION OF STORE COHERENCE RELATIVE TO PAGE TRANSLATION INVALIDA...

TEST CASE GENERATION FOR A HARDWARE STATE SPACE

CONTROLLING SEGMENT LAYOUT IN A STRESS TEST FOR A PROCESSOR MEMORY...

METHOD, SYSTEM, AND APPARATUS FOR STRESS TESTING MEMORY TRANSLATION...

System and Method for Testing Processor Errors

LIST INSERTION IN TEST SEGMENTS WITH NON-NATURALLY ALIGNED DATA BOU...

EFFICIENTLY GENERATING EFFECTIVE ADDRESS TRANSLATIONS FOR MEMORY MA...

LIST INSERTION IN TEST SEGMENTS WITH NON-NATURALLY ALIGNED DATA BOU...

METHOD, SYSTEM, AND APPARATUS FOR STRESS TESTING MEMORY TRANSLATION...

VALIDATION OF CORRECTNESS OF INTERRUPT TRIGGERS AND DELIVERY

EFFICIENT TESTING OF DIRECT MEMORY ADDRESS TRANSLATION

EFFICIENT TESTING OF DIRECT MEMORY ADDRESS TRANSLATION

STRESS TESTING A PROCESSOR MEMORY WITH A LINK STACK

STRESS TESTING A PROCESSOR MEMORY WITH A LINK STACK

REPLICATING TEST CASE DATA INTO A CACHE WITH NON-NATURALLY ALIGNED...

TESTING SPECULATIVE INSTRUCTION EXECUTION WITH TEST CASES PLACED IN...

IDENTIFYING STALE ENTRIES IN ADDRESS TRANSLATION CACHE

EFFICIENT VALIDATION OF TRANSACTIONAL MEMORY IN A COMPUTER PROCESSOR

EFFICIENTLY GENERATING EFFECTIVE ADDRESS TRANSLATIONS FOR MEMORY MA...

REPLICATING TEST CASE DATA INTO A CACHE AND CACHE INHIBITED MEMORY

CORE PAIRING IN MULTICORE SYSTEMS

SYNCHRONIZATION OF HARDWARE AGENTS IN A COMPUTER SYSTEM

REPLICATING TEST CODE AND TEST DATA INTO A CACHE WITH NON-NATURALLY...

EFFICIENT VALIDATION/VERIFICATION OF COHERENCY AND SNOOP FILTERING...

REPLICATING TEST CASE DATA INTO A CACHE WITH NON-NATURALLY ALIGNED...

REPLICATING TEST CASE DATA INTO A CACHE WITH NON-NATURALLY ALIGNED...