Manoj Khare

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for reducing memory latency in a cache coheren...
- Patent number 7,996,625
- Issue date Aug 9, 2011
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable processor apparatus integrating dedicated search regis...
- Patent number 7,464,254
- Issue date Dec 9, 2008
- Cisco Technology, Inc.
- Harshvardhan Sharangpani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing memory latency in a cache coheren...
- Patent number 7,234,029
- Issue date Jun 19, 2007
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for handling explicit writeback in a cache coherent multi...
- Patent number 7,167,957
- Issue date Jan 23, 2007
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for pipelining ordered input/output transactio...
- Patent number 7,124,252
- Issue date Oct 17, 2006
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for evaluation of regular expressions of ar...
- Patent number 7,085,918
- Issue date Aug 1, 2006
- Cisco Systems, Inc.
- Harshvardan Sharangpani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for handling I/O transactions with known transaction leng...
- Patent number 6,976,129
- Issue date Dec 13, 2005
- Intel Corporation
- Kenneth C. Creta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for managing transaction requests in a multi-n...
- Patent number 6,971,098
- Issue date Nov 29, 2005
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for initiating an implicit write-back in response to a re...
- Patent number 6,859,864
- Issue date Feb 22, 2005
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for handling explicit writeback in a cache coherent multi...
- Patent number 6,842,830
- Issue date Jan 11, 2005
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for preventing starvation in a multi-node arch...
- Patent number 6,826,619
- Issue date Nov 30, 2004
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for centralized snoop filtering
- Patent number 6,810,467
- Issue date Oct 26, 2004
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for invalidating a cache line without data ret...
- Patent number 6,772,298
- Issue date Aug 3, 2004
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for handling conflicts in a multi-node computer architecture
- Patent number 6,622,215
- Issue date Sep 16, 2003
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed mechanism for resolving cache coherence conflicts in a...
- Patent number 6,615,319
- Issue date Sep 2, 2003
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for preventing starvation in a multi-node arch...
- Patent number 6,487,643
- Issue date Nov 26, 2002
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for efficient read prefetching of instruction...
- Patent number 5,367,657
- Issue date Nov 22, 1994
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method and apparatus for reducing memory latency in a cache coheren...
- Publication number 20070204111
- Publication date Aug 30, 2007
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for handling explicit writeback in a cache coherent multi...
- Publication number 20060106993
- Publication date May 18, 2006
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatuses for evaluation of regular expressions of ar...
- Publication number 20050012521
- Publication date Jan 20, 2005
- Harshvardhan Sharangpani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for handling explicit writeback in a cache coherent multi...
- Publication number 20040268061
- Publication date Dec 30, 2004
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable processor apparatus integrating dedicated search regis...
- Publication number 20040215593
- Publication date Oct 28, 2004
- Harshvardhan Sharangpani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for handling I/O transactions with known transaction leng...
- Publication number 20040064652
- Publication date Apr 1, 2004
- Kenneth C. Creta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for initiating an implicit write-back in response to a re...
- Publication number 20030131202
- Publication date Jul 10, 2003
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for efficiently supporting the full MESI (modified, exclu...
- Publication number 20030131201
- Publication date Jul 10, 2003
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for managing transaction requests in a multi-n...
- Publication number 20030005167
- Publication date Jan 2, 2003
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for handling explicit writeback in a cache coherent multi...
- Publication number 20020178210
- Publication date Nov 28, 2002
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for handling conflicts in a multi-node computer architecture
- Publication number 20020129206
- Publication date Sep 12, 2002
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for reducing memory latency in a cache coheren...
- Publication number 20020087811
- Publication date Jul 4, 2002
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to implement a locked-bus transaction
- Publication number 20020087766
- Publication date Jul 4, 2002
- Akhilesh Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Distributed mechanism for resolving cache coherence conflicts in a...
- Publication number 20020087804
- Publication date Jul 4, 2002
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for completing purge requests or the like in a mu...
- Publication number 20020087765
- Publication date Jul 4, 2002
- Akhilesh Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR INTERRUPT DELIVERY
- Publication number 20020087775
- Publication date Jul 4, 2002
- Lily P. Looi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for invalidating a cache line without data ret...
- Publication number 20020078305
- Publication date Jun 20, 2002
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING

Manoj Khare

Person

Patents Grantslast 30 patents

Method and apparatus for reducing memory latency in a cache coheren...

Programmable processor apparatus integrating dedicated search regis...

Method and apparatus for reducing memory latency in a cache coheren...

Mechanism for handling explicit writeback in a cache coherent multi...

Method and apparatus for pipelining ordered input/output transactio...

Methods and apparatuses for evaluation of regular expressions of ar...

Mechanism for handling I/O transactions with known transaction leng...

Method and apparatus for managing transaction requests in a multi-n...

Mechanism for initiating an implicit write-back in response to a re...

Mechanism for handling explicit writeback in a cache coherent multi...

Method and apparatus for preventing starvation in a multi-node arch...

Method and apparatus for centralized snoop filtering

Method and apparatus for invalidating a cache line without data ret...

Mechanism for handling conflicts in a multi-node computer architecture

Distributed mechanism for resolving cache coherence conflicts in a...

Method and apparatus for preventing starvation in a multi-node arch...

Method and apparatus for efficient read prefetching of instruction...

Patents Applicationslast 30 patents

Method and apparatus for reducing memory latency in a cache coheren...

Mechanism for handling explicit writeback in a cache coherent multi...

Methods and apparatuses for evaluation of regular expressions of ar...

Mechanism for handling explicit writeback in a cache coherent multi...

Programmable processor apparatus integrating dedicated search regis...

Mechanism for handling I/O transactions with known transaction leng...

Mechanism for initiating an implicit write-back in response to a re...

Mechanism for efficiently supporting the full MESI (modified, exclu...

Method and apparatus for managing transaction requests in a multi-n...

Mechanism for handling explicit writeback in a cache coherent multi...

Mechanism for handling conflicts in a multi-node computer architecture

Method and apparatus for reducing memory latency in a cache coheren...

Method and apparatus to implement a locked-bus transaction

Distributed mechanism for resolving cache coherence conflicts in a...

Method and system for completing purge requests or the like in a mu...

APPARATUS AND METHOD FOR INTERRUPT DELIVERY

Method and apparatus for invalidating a cache line without data ret...