Manuel Beck

Person

Kirchheim unter Teck, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Floorplan of a design for an integrated circuit
- Patent number 11,568,633
- Issue date Jan 31, 2023
- International Business Machines Corporation
- Siegmund Schlechter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Designing semiconductor circuit test elements
- Patent number 11,055,461
- Issue date Jul 6, 2021
- International Business Machines Corporation
- Manuel Beck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement and timing aware wire tagging
- Patent number 10,719,654
- Issue date Jul 21, 2020
- International Business Machines Corporation
- Manuel Beck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enabling automatic staging for nets or net groups with VHDL attributes
- Patent number 10,572,618
- Issue date Feb 25, 2020
- International Business Machines Corporation
- Manuel Beck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for addition of multiple binary numbers
- Patent number 10,528,323
- Issue date Jan 7, 2020
- International Business Machines Corporation
- Manuel Beck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing of nets of an integrated circuit
- Patent number 10,452,800
- Issue date Oct 22, 2019
- International Business Machines Corporation
- Manuel Beck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing of nets of an integrated circuit
- Patent number 10,452,801
- Issue date Oct 22, 2019
- International Business Machines Corporation
- Manuel Beck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for addition of multiple binary numbers
- Patent number 10,168,991
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Manuel Beck
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
REINFORCEMENT LEARNING BASED CORRECTION OF TIMING FAILURES
- Publication number 20240232503
- Publication date Jul 11, 2024
- International Business Machines Corporation
- Gregor Boronowsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REINFORCEMENT LEARNING BASED CORRECTION OF TIMING FAILURES
- Publication number 20240135083
- Publication date Apr 25, 2024
- International Business Machines Corporation
- Gregor Boronowsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLOORPLAN OF A DESIGN FOR AN INTEGRATED CIRCUIT
- Publication number 20210287036
- Publication date Sep 16, 2021
- International Business Machines Corporation
- Siegmund Schlechter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLACEMENT AND TIMING AWARE WIRE TAGGING
- Publication number 20190163862
- Publication date May 30, 2019
- International Business Machines Corporation
- Manuel Beck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENABLING AUTOMATIC STAGING FOR NETS OR NET GROUPS WITH VHDL ATTRIBUTES
- Publication number 20190163854
- Publication date May 30, 2019
- International Business Machines Corporation
- Manuel Beck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT FOR ADDITION OF MULTIPLE BINARY NUMBERS
- Publication number 20190034165
- Publication date Jan 31, 2019
- International Business Machines Corporation
- Manuel BECK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT FOR ADDITION OF MULTIPLE BINARY NUMBERS
- Publication number 20180088907
- Publication date Mar 29, 2018
- International Business Machines Corporation
- Manuel BECK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROUTING OF NETS OF AN INTEGRATED CIRCUIT
- Publication number 20160371418
- Publication date Dec 22, 2016
- International Business Machines Corporation
- Manuel Beck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROUTING OF NETS OF AN INTEGRATED CIRCUIT
- Publication number 20160371401
- Publication date Dec 22, 2016
- International Business Machines Corporation
- Manuel Beck
- G06 - COMPUTING CALCULATING COUNTING

Manuel Beck

Person

Patents Grantslast 30 patents

Floorplan of a design for an integrated circuit

Designing semiconductor circuit test elements

Placement and timing aware wire tagging

Enabling automatic staging for nets or net groups with VHDL attributes

Circuit for addition of multiple binary numbers

Routing of nets of an integrated circuit

Routing of nets of an integrated circuit

Circuit for addition of multiple binary numbers

Patents Applicationslast 30 patents

REINFORCEMENT LEARNING BASED CORRECTION OF TIMING FAILURES

REINFORCEMENT LEARNING BASED CORRECTION OF TIMING FAILURES

FLOORPLAN OF A DESIGN FOR AN INTEGRATED CIRCUIT

PLACEMENT AND TIMING AWARE WIRE TAGGING

ENABLING AUTOMATIC STAGING FOR NETS OR NET GROUPS WITH VHDL ATTRIBUTES

CIRCUIT FOR ADDITION OF MULTIPLE BINARY NUMBERS

CIRCUIT FOR ADDITION OF MULTIPLE BINARY NUMBERS

ROUTING OF NETS OF AN INTEGRATED CIRCUIT

ROUTING OF NETS OF AN INTEGRATED CIRCUIT