Marat GERSHOIG

Person

Ottawa, CA

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for conducting built-in self-test of memory macro
- Patent number 12,033,710
- Issue date Jul 9, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ted Wong
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan architecture for interconnect testing in 3D integrated circuits
- Patent number 11,899,064
- Issue date Feb 13, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
Conducting built-in self-test of memory macro
- Patent number 11,823,758
- Issue date Nov 21, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Saman Adham
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan architecture for interconnect testing in 3D integrated circuits
- Patent number 11,549,984
- Issue date Jan 10, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
Scan architecture for interconnect testing in 3D integrated circuits
- Patent number 10,539,617
- Issue date Jan 21, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR CONDUCTING BUILT-IN SELF-TEST OF MEMORY MACRO
- Publication number 20240321377
- Publication date Sep 26, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ted Wong
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
- Publication number 20240133951
- Publication date Apr 25, 2024
- TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Sandeep Kumar GOEL
- G01 - MEASURING TESTING
Information Patent Application
CONDUCTING BUILT-IN SELF-TEST OF MEMORY MACRO
- Publication number 20240055066
- Publication date Feb 15, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ted Wong
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
- Publication number 20230113905
- Publication date Apr 13, 2023
- TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Sandeep Kumar GOEL
- G01 - MEASURING TESTING
Information Patent Application
CONDUCTING BUILT-IN SELF-TEST OF MEMORY MACRO
- Publication number 20220254428
- Publication date Aug 11, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Saman Adham
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR CONDUCTING BUILT-IN SELF-TEST OF MEMORY MACRO
- Publication number 20220254429
- Publication date Aug 11, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ted Wong
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
- Publication number 20200124668
- Publication date Apr 23, 2020
- Sandeep Kumar GOEL
- G01 - MEASURING TESTING
Information Patent Application
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
- Publication number 20170350939
- Publication date Dec 7, 2017
- Taiwan Semiconductor Manufacturing Co., LTD
- Sandeep Kumar GOEL
- G01 - MEASURING TESTING

Marat GERSHOIG

Person

Patents Grantslast 30 patents

System and method for conducting built-in self-test of memory macro

Scan architecture for interconnect testing in 3D integrated circuits

Conducting built-in self-test of memory macro

Scan architecture for interconnect testing in 3D integrated circuits

Scan architecture for interconnect testing in 3D integrated circuits

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR CONDUCTING BUILT-IN SELF-TEST OF MEMORY MACRO

SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS

CONDUCTING BUILT-IN SELF-TEST OF MEMORY MACRO

SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS

CONDUCTING BUILT-IN SELF-TEST OF MEMORY MACRO

SYSTEM AND METHOD FOR CONDUCTING BUILT-IN SELF-TEST OF MEMORY MACRO

SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS

SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS