Marat TEPLITSKY

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Rishon Le-Zion, IL

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Patents Grantslast 30 patents

Information Patent Grant
Method and system for automatically generating executable system-le...
- Patent number 9,582,406
- Issue date Feb 28, 2017
- Cadence Design Systems, Inc.
- Marat Teplitsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coverage driven generation of constrained random stimuli
- Patent number 9,514,035
- Issue date Dec 6, 2016
- Cadence Design Systems, Inc.
- Marat Teplitsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for debugging a program that includes declarative...
- Patent number 9,239,773
- Issue date Jan 19, 2016
- Cadence Design Systems, Inc.
- Marat Teplitsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and computer program product for constraint solving
- Patent number 9,189,743
- Issue date Nov 17, 2015
- Cadence Design Systems, Inc.
- Marat Teplitsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for test reduction and analysis
- Patent number 8,719,771
- Issue date May 6, 2014
- Cadence Design Systems, Inc.
- Meir Ovadia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automation of software verification
- Patent number 8,156,474
- Issue date Apr 10, 2012
- Cadence Design Systems, Inc.
- Marat Teplitsky
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM FOR TEST REDUCTION AND ANALYSIS
- Publication number 20110078651
- Publication date Mar 31, 2011
- Cadence Design Systems, Inc.
- Meir OVADIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATION OF SOFTWARE VERIFICATION
- Publication number 20090172649
- Publication date Jul 2, 2009
- Cadence Design System, Inc.
- Marat Teplitsky
- G06 - COMPUTING CALCULATING COUNTING