Marc Torrant

Person

Sacramento, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Energy-efficient core voltage selection apparatus and method
- Patent number 12,073,227
- Issue date Aug 27, 2024
- Intel Corporation
- Noor Mubeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Isochronous agent data pinning in a multi-level memory system
- Patent number 9,542,336
- Issue date Jan 10, 2017
- Intel Corporation
- Marc Torrant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method to dynamically expand associativity of a cache...
- Patent number 9,514,047
- Issue date Dec 6, 2016
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Execution context swap between heterogeneous functional hardware units
- Patent number 9,250,901
- Issue date Feb 2, 2016
- Intel Corporation
- Inder M. Sodhi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Writeback mechanisms for improving far memory utilization in multi-...
- Patent number 9,032,099
- Issue date May 12, 2015
- Intel Corporation
- Jorge E. Parra
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HYBRID PERFORMANCE MONITORING UNIT (PMU) ENUMERATION
- Publication number 20240111654
- Publication date Apr 4, 2024
- Intel Corporation
- Raoul Rivas Toledano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENERGY-EFFICIENT CORE VOLTAGE SELECTION APPARATUS AND METHOD
- Publication number 20220058029
- Publication date Feb 24, 2022
- Intel Corporation
- Noor Mubeen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GUARANTEED QUALITY OF SERVICE IN SYSTEM-ON-A-CHIP UNCORE FABRIC
- Publication number 20160188529
- Publication date Jun 30, 2016
- Intel Corporation
- Ramadass Nagarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Method to Dynamically Expand Associativity of A Cache...
- Publication number 20160179666
- Publication date Jun 23, 2016
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZED WRITE ALLOCATION FOR TWO-LEVEL MEMORY
- Publication number 20150178203
- Publication date Jun 25, 2015
- Marc Torrant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ISOCHRONOUS AGENT DATA PINNING IN A MULTI-LEVEL MEMORY SYSTEM
- Publication number 20150169439
- Publication date Jun 18, 2015
- Marc Torrant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXECUTION CONTEXT SWAP BETWEEN HETEROGENOUS FUNCTIONAL HARDWARE UNITS
- Publication number 20140281380
- Publication date Sep 18, 2014
- Inder M. Sodhi
- G06 - COMPUTING CALCULATING COUNTING

Marc Torrant

Person

Patents Grantslast 30 patents

Energy-efficient core voltage selection apparatus and method

Isochronous agent data pinning in a multi-level memory system

Apparatus and method to dynamically expand associativity of a cache...

Execution context swap between heterogeneous functional hardware units

Writeback mechanisms for improving far memory utilization in multi-...

Patents Applicationslast 30 patents

HYBRID PERFORMANCE MONITORING UNIT (PMU) ENUMERATION

ENERGY-EFFICIENT CORE VOLTAGE SELECTION APPARATUS AND METHOD

GUARANTEED QUALITY OF SERVICE IN SYSTEM-ON-A-CHIP UNCORE FABRIC

Apparatus and Method to Dynamically Expand Associativity of A Cache...

OPTIMIZED WRITE ALLOCATION FOR TWO-LEVEL MEMORY

ISOCHRONOUS AGENT DATA PINNING IN A MULTI-LEVEL MEMORY SYSTEM

EXECUTION CONTEXT SWAP BETWEEN HETEROGENOUS FUNCTIONAL HARDWARE UNITS