Marco Burzio

Person

Turin, IT

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit phase-locked loop charge pump
- Patent number 6,292,039
- Issue date Sep 18, 2001
- Telecom Italia Lab S.P.A.
- Marco Burzio
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PLL having circuits for selecting optimum VCO input/output characte...
- Patent number 6,259,327
- Issue date Jul 10, 2001
- CSELT - Centro Studi e Laboratori Telecomunicazioni SpA
- Emanuele Balistreri
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High tunability CMOS delay element
- Patent number 6,255,881
- Issue date Jul 3, 2001
- CSELT - Centro Studi e Laboratori Telecomunicazioni SpA
- Emanuele Balistreri
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Device for compensating process and operating parameter variations...
- Patent number 6,218,886
- Issue date Apr 17, 2001
- CSELT - Centro Studi e Laboratori Telecomunicazioni SpA
- Emanuele Balistreri
- G05 - CONTROLLING REGULATING
Information Patent Grant
CMOS circuit for generating a current reference, the circuit compri...
- Patent number 6,166,587
- Issue date Dec 26, 2000
- CSELT - Centro Studi e Laboratori Telecomunicazioni S.p.A.
- Marco Burzio
- G05 - CONTROLLING REGULATING
Information Patent Grant
Phase locked loop having control circuit for automatically operatin...
- Patent number 6,127,896
- Issue date Oct 3, 2000
- CSELT - Centro Studi e Laboratori Telecomunicazioni S.p.A.
- Marco Burzio
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Device for and method of aligning in time digital signals, for exam...
- Patent number 6,067,334
- Issue date May 23, 2000
- CSELT - Centro Studi e Laboratori Telecomunicazioni S.p.A.
- Bruno Bostica
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuit in CMOS technology for high speed driving of optical sources
- Patent number 5,828,246
- Issue date Oct 27, 1998
- Cselt Studi E Laboratori Telecomuni-Cazioni S.P.A.
- Bruno Bostica
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Serializing-parallelizing circuit for high speed digital signals
- Patent number 5,790,058
- Issue date Aug 4, 1998
- CSELT - Centro Studi e Laboratori Telecomunicazioni S.p.A.
- Marco Burzio
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuit for clock signal extraction from a high speed data stream
- Patent number 5,686,849
- Issue date Nov 11, 1997
- CSELT Centro Studi e Laboratori Telecomunicazioni S.p.A.
- Marco Burzio
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Marco Burzio

Person

Patents Grantslast 30 patents

Integrated circuit phase-locked loop charge pump

PLL having circuits for selecting optimum VCO input/output characte...

High tunability CMOS delay element

Device for compensating process and operating parameter variations...

CMOS circuit for generating a current reference, the circuit compri...

Phase locked loop having control circuit for automatically operatin...

Device for and method of aligning in time digital signals, for exam...

Circuit in CMOS technology for high speed driving of optical sources

Serializing-parallelizing circuit for high speed digital signals

Circuit for clock signal extraction from a high speed data stream