Marco Ferrario

Person

Milano, IT

People

Patents Grantslast 30 patents

Information Patent Grant
Timing violation handling in a synchronous interface memory
- Patent number 9,558,799
- Issue date Jan 31, 2017
- Micron Technology, Inc.
- Marco Ferrario
- G11 - INFORMATION STORAGE
Information Patent Grant
Timing violation handling in a synchronous interface memory
- Patent number 9,208,835
- Issue date Dec 8, 2015
- Micron Technology, Inc.
- Marco Ferrario
- G11 - INFORMATION STORAGE
Information Patent Grant
Indexed register access for memory device
- Patent number 8,832,392
- Issue date Sep 9, 2014
- Micron Technology, Inc.
- Marco Ferrario
- G11 - INFORMATION STORAGE
Information Patent Grant
Indexed register access for memory device
- Patent number 8,539,189
- Issue date Sep 17, 2013
- Micron Technology, Inc.
- Marco Ferrario
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device employing three-level cells and related methods of ma...
- Patent number 7,596,023
- Issue date Sep 29, 2009
- Alessandro Magnavacca
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with a ramp-like voltage biasing structure based on a...
- Patent number 7,359,246
- Issue date Apr 15, 2008
- STMicroelectronics S.r.l.
- Marco Sforzin
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming method of multilevel memories and corresponding circuit
- Patent number 7,317,637
- Issue date Jan 8, 2008
- STMicroelectronics S.r.l.
- Emanuele Confalonieri
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and device for timing random reading of a memory device
- Patent number 6,956,787
- Issue date Oct 18, 2005
- STMicroelectronics S.r.l.
- Carlo Lisi
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
TIMING VIOLATION HANDLING IN A SYNCHRONOUS INTERFACE MEMORY
- Publication number 20160086662
- Publication date Mar 24, 2016
- Micron Technology, Inc.
- Marco Ferrario
- G11 - INFORMATION STORAGE
Information Patent Application
INDEXED REGISTER ACCESS FOR MEMORY DEVICE
- Publication number 20140019702
- Publication date Jan 16, 2014
- Micron Technology, Inc.
- Marco Ferrario
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING VIOLATION HANDLING IN A SYNCHRONOUS INTERFACE MEMORY
- Publication number 20130077393
- Publication date Mar 28, 2013
- Marco Ferrario
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RELIABLE WRITE FOR NON-VOLATILE MEMORY
- Publication number 20120137093
- Publication date May 31, 2012
- Micron Technology, Inc.
- Marco Ferrario
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INDEXED REGISTER ACCESS FOR MEMORY DEVICE
- Publication number 20110271038
- Publication date Nov 3, 2011
- Micron Technology, Inc.
- Marco Ferrario
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE EMPLOYING THREE-LEVEL CELLS AND RELATED METHODS OF MA...
- Publication number 20080106937
- Publication date May 8, 2008
- STMicroelectronics S.r.I.
- Alessandro MAGNAVACCA
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device with a ramp-like voltage biasing structure based on a...
- Publication number 20060198187
- Publication date Sep 7, 2006
- STMicroelectronics S.r.l.
- Marco Sforzin
- G11 - INFORMATION STORAGE
Information Patent Application
Programming method of multilevel memories and corresponding circuit
- Publication number 20060120161
- Publication date Jun 8, 2006
- STMicroelectronics S.r. I.
- Emanuele Confalonieri
- G11 - INFORMATION STORAGE
Information Patent Application
Method and device for timing random reading of a memory device
- Publication number 20040151035
- Publication date Aug 5, 2004
- Carlo Lisi
- G11 - INFORMATION STORAGE

Marco Ferrario

Person

Patents Grantslast 30 patents

Timing violation handling in a synchronous interface memory

Timing violation handling in a synchronous interface memory

Indexed register access for memory device

Indexed register access for memory device

Memory device employing three-level cells and related methods of ma...

Memory device with a ramp-like voltage biasing structure based on a...

Programming method of multilevel memories and corresponding circuit

Method and device for timing random reading of a memory device

Patents Applicationslast 30 patents

TIMING VIOLATION HANDLING IN A SYNCHRONOUS INTERFACE MEMORY

INDEXED REGISTER ACCESS FOR MEMORY DEVICE

TIMING VIOLATION HANDLING IN A SYNCHRONOUS INTERFACE MEMORY

RELIABLE WRITE FOR NON-VOLATILE MEMORY

INDEXED REGISTER ACCESS FOR MEMORY DEVICE

MEMORY DEVICE EMPLOYING THREE-LEVEL CELLS AND RELATED METHODS OF MA...

Memory device with a ramp-like voltage biasing structure based on a...

Programming method of multilevel memories and corresponding circuit

Method and device for timing random reading of a memory device