MARIANO LAYSON CHING JR.

Person

Tianjin, CN

People

Patents Grantslast 30 patents

Information Patent Grant
Cavity formed in a molding compound of a semiconductor package to r...
- Patent number 11,984,408
- Issue date May 14, 2024
- NXP USA, INC.
- You Ge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lead-frame assembly, semiconductor package and methods for improved...
- Patent number 11,923,275
- Issue date Mar 5, 2024
- NXP USA, INC.
- Allen Marfil Descartin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lead frame with selective patterned plating
- Patent number 10,847,449
- Issue date Nov 24, 2020
- NXP USA, INC.
- Meijiang Song
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid lead frame for semiconductor die package with improved creep...
- Patent number 10,734,311
- Issue date Aug 4, 2020
- NXP USA, INC.
- Mariano Layson Ching
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lead reduction for improved creepage distance
- Patent number 10,734,327
- Issue date Aug 4, 2020
- NXP USA, INC.
- Mariano Layson Ching
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged integrated circuit having stacked die and method for therefor
- Patent number 10,446,476
- Issue date Oct 15, 2019
- NXP USA, INC.
- Leo M. Higgins
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pressure-sensing integrated circuit device with diaphragm
- Patent number 10,151,658
- Issue date Dec 11, 2018
- NXP USA, INC.
- Mariano Layson Ching
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lead frame and substrate semiconductor package
- Patent number 9,190,353
- Issue date Nov 17, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Mariano Layson Ching
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CAVITY FORMED IN A MOLDING COMPOUND OF A SEMICONDUCTOR PACKAGE TO R...
- Publication number 20230124619
- Publication date Apr 20, 2023
- You Ge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEAD-FRAME ASSEMBLY, SEMICONDUCTOR PACKAGE AND METHODS FOR IMPROVED...
- Publication number 20220415761
- Publication date Dec 29, 2022
- NXP USA, Inc.
- Allen Marfil Descartin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID LEAD FRAME FOR SEMICONDUCTOR DIE PACKAGE WITH IMPROVED CREEP...
- Publication number 20200203262
- Publication date Jun 25, 2020
- NXP USA, Inc.
- Mariano Layson CHING
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEAD REDUCTION FOR IMPROVED CREEPAGE DISTANCE
- Publication number 20200203289
- Publication date Jun 25, 2020
- NXP USA, Inc.
- Mariano Layson CHING
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEAD FRAME WITH SELECTIVE PATTERNED PLATING
- Publication number 20200203258
- Publication date Jun 25, 2020
- NXP USA, Inc.
- Meijiang Song
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED INTEGRATED CIRCUIT HAVING STACKED DIE AND METHOD FOR THEREFOR
- Publication number 20190088576
- Publication date Mar 21, 2019
- NXP USA, Inc.
- LEO M. HIGGINS
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PRESSURE-SENSING INTEGRATED CIRCUIT DEVICE WITH DIAPHRAGM
- Publication number 20170292884
- Publication date Oct 12, 2017
- NXP USA, Inc.
- MARIANO LAYSON CHING
- G01 - MEASURING TESTING
Information Patent Application
LEAD FRAME AND SUBSTRATE SEMICONDUCTOR PACKAGE
- Publication number 20140252581
- Publication date Sep 11, 2014
- MARIANO LAYSON CHING
- H01 - BASIC ELECTRIC ELEMENTS

MARIANO LAYSON CHING JR.

Person

Patents Grantslast 30 patents

Cavity formed in a molding compound of a semiconductor package to r...

Lead-frame assembly, semiconductor package and methods for improved...

Lead frame with selective patterned plating

Hybrid lead frame for semiconductor die package with improved creep...

Lead reduction for improved creepage distance

Packaged integrated circuit having stacked die and method for therefor

Pressure-sensing integrated circuit device with diaphragm

Lead frame and substrate semiconductor package

Patents Applicationslast 30 patents

CAVITY FORMED IN A MOLDING COMPOUND OF A SEMICONDUCTOR PACKAGE TO R...

LEAD-FRAME ASSEMBLY, SEMICONDUCTOR PACKAGE AND METHODS FOR IMPROVED...

HYBRID LEAD FRAME FOR SEMICONDUCTOR DIE PACKAGE WITH IMPROVED CREEP...

LEAD REDUCTION FOR IMPROVED CREEPAGE DISTANCE

LEAD FRAME WITH SELECTIVE PATTERNED PLATING

PACKAGED INTEGRATED CIRCUIT HAVING STACKED DIE AND METHOD FOR THEREFOR

PRESSURE-SENSING INTEGRATED CIRCUIT DEVICE WITH DIAPHRAGM

LEAD FRAME AND SUBSTRATE SEMICONDUCTOR PACKAGE