Mario A. Rivas

Person

West Palm Beach, FL, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multipart analog message and a response in a communication system
- Patent number 5,905,448
- Issue date May 18, 1999
- Motorola, Inc.
- Alain Charles Briancon
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Tolerance accumulating circuit supporting mechanical shock isolator
- Patent number 5,369,399
- Issue date Nov 29, 1994
- Motorola, Inc.
- David A. Tribbey
- G08 - SIGNALLING
Information Patent Grant
Circuit supporting mechanical shock isolator for radio receiver
- Patent number 5,317,308
- Issue date May 31, 1994
- Motorola, Inc.
- David A. Tribbey
- G08 - SIGNALLING
Information Patent Grant
Pager receiver with selective operating voltage and reduced power c...
- Patent number 5,218,705
- Issue date Jun 8, 1993
- Motorola, Inc.
- Michael J. DeLuca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computing system with selective operating voltage and bus speed
- Patent number 5,086,501
- Issue date Feb 4, 1992
- Motorola, Inc.
- Michael J. DeLuca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequency synthesizer with an interface controller and buffer memory
- Patent number 4,901,036
- Issue date Feb 13, 1990
- Motorola, Inc.
- Barry W. Herold
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Timer architecture for multi-task computers and for serial data dec...
- Patent number 4,879,733
- Issue date Nov 7, 1989
- Motorola, Inc.
- Kenneth R. Burch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Paging receiver having selectively protected regions of memory
- Patent number 4,839,628
- Issue date Jun 13, 1989
- Motorola, Inc.
- Walter L. Davis
- G08 - SIGNALLING

Mario A. Rivas

Person

Patents Grantslast 30 patents

Multipart analog message and a response in a communication system

Tolerance accumulating circuit supporting mechanical shock isolator

Circuit supporting mechanical shock isolator for radio receiver

Pager receiver with selective operating voltage and reduced power c...

Computing system with selective operating voltage and bus speed

Frequency synthesizer with an interface controller and buffer memory

Timer architecture for multi-task computers and for serial data dec...

Paging receiver having selectively protected regions of memory