Mario Allegra

Person

Milan, IT

People

Patents Grantslast 30 patents

Information Patent Grant
Adaptive write operations for a memory device
- Patent number 11,942,183
- Issue date Mar 26, 2024
- Micron Technology, Inc.
- Mattia Boniardi
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementations to store fuse data in memory devices
- Patent number 11,837,267
- Issue date Dec 5, 2023
- Micron Technology, Inc.
- Mattia Boniardi
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques to access a self-selecting memory device
- Patent number 11,763,886
- Issue date Sep 19, 2023
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Chalcogenide-based memory architecture
- Patent number 11,283,016
- Issue date Mar 22, 2022
- Intel Corporation
- Mario Allegra
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive write operations for a memory device
- Patent number 11,158,358
- Issue date Oct 26, 2021
- Micron Technology, Inc.
- Mattia Boniardi
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques to access a self-selecting memory device
- Patent number 11,152,065
- Issue date Oct 19, 2021
- Micron Technology, Inc.
- Innocenzo Tortorelli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dedicated read voltages for data structures
- Patent number 11,114,159
- Issue date Sep 7, 2021
- Micron Technology, Inc.
- Marco Sforzin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementations to store fuse data in memory devices
- Patent number 11,037,613
- Issue date Jun 15, 2021
- Micron Technology, Inc.
- Mattia Boniardi
- G11 - INFORMATION STORAGE
Information Patent Grant
Chalcogenide-based memory architecture
- Patent number 10,763,432
- Issue date Sep 1, 2020
- Intel Corporation
- Mario Allegra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell architecture for multilevel cell programming
- Patent number 10,714,177
- Issue date Jul 14, 2020
- Micron Technology, Inc.
- Mario Allegra
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques to access a self-selecting memory device
- Patent number 10,665,298
- Issue date May 26, 2020
- Micron Technology, Inc.
- Innocenzo Tortorelli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dedicated read voltages for data structures
- Patent number 10,658,034
- Issue date May 19, 2020
- Micron Technology, Inc.
- Marco Sforzin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to access a self-selecting memory device
- Patent number 10,381,075
- Issue date Aug 13, 2019
- Micron Technology, Inc.
- Innocenzo Totorelli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell architecture for multilevel cell programming
- Patent number 10,311,954
- Issue date Jun 4, 2019
- Micron Technology, Inc.
- Mario Allegra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell architecture for multilevel cell programming
- Patent number 10,049,737
- Issue date Aug 14, 2018
- Micron Technology, Inc.
- Mario Allegra
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell architecture for multilevel cell programming
- Patent number 9,607,691
- Issue date Mar 28, 2017
- Micron Technology, Inc.
- Mario Allegra
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ADAPTIVE WRITE OPERATIONS FOR A MEMORY DEVICE
- Publication number 20240203468
- Publication date Jun 20, 2024
- Micron Technology, Inc.
- Mattia Boniardi
- G11 - INFORMATION STORAGE
Information Patent Application
PHASE-CHANGE MEMORY CELL WITH ASYMMETRIC STRUCTURE, A MEMORY DEVICE...
- Publication number 20230240160
- Publication date Jul 27, 2023
- STMicroelectronics S.r.l
- Mario ALLEGRA
Information Patent Application
TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE
- Publication number 20220115068
- Publication date Apr 14, 2022
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE WRITE OPERATIONS FOR A MEMORY DEVICE
- Publication number 20220108732
- Publication date Apr 7, 2022
- Micron Technology, Inc.
- Mattia Boniardi
- G11 - INFORMATION STORAGE
Information Patent Application
IMPLEMENTATIONS TO STORE FUSE DATA IN MEMORY DEVICES
- Publication number 20210272615
- Publication date Sep 2, 2021
- Micron Technology, Inc.
- Mattia Boniardi
- G11 - INFORMATION STORAGE
Information Patent Application
CHALCOGENIDE-BASED MEMORY ARCHITECTURE
- Publication number 20210050519
- Publication date Feb 18, 2021
- Intel Corporation
- Mario Allegra
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE WRITE OPERATIONS FOR A MEMORY DEVICE
- Publication number 20210027813
- Publication date Jan 28, 2021
- Micron Technology, Inc.
- Mattia Boniardi
- G11 - INFORMATION STORAGE
Information Patent Application
IMPLEMENTATIONS TO STORE FUSE DATA IN MEMORY DEVICES
- Publication number 20210020218
- Publication date Jan 21, 2021
- Micron Technology, Inc.
- Mattia Boniardi
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE
- Publication number 20200327940
- Publication date Oct 15, 2020
- Micron Technology, Inc.
- Innocenzo Tortorelli
- G11 - INFORMATION STORAGE
Information Patent Application
DEDICATED READ VOLTAGES FOR DATA STRUCTURES
- Publication number 20200279604
- Publication date Sep 3, 2020
- Micron Technology, Inc.
- Marco Sforzin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHALCOGENIDE-BASED MEMORY ARCHITECTURE
- Publication number 20200194670
- Publication date Jun 18, 2020
- Intel Corporation
- Mario Allegra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEDICATED READ VOLTAGES FOR DATA STRUCTURES
- Publication number 20200143880
- Publication date May 7, 2020
- Micron Technology, Inc.
- Marco Sforzin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE
- Publication number 20190362789
- Publication date Nov 28, 2019
- Micron Technology, Inc.
- Innocenzo Tortorelli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL ARCHITECTURE FOR MULTILEVEL CELL PROGRAMMING
- Publication number 20190244665
- Publication date Aug 8, 2019
- Micron Technology, Inc.
- Mario Allegra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE
- Publication number 20190189206
- Publication date Jun 20, 2019
- Micron Technology, Inc.
- Innocenzo Tortorelli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL ARCHITECTURE FOR MULTILEVEL CELL PROGRAMMING
- Publication number 20180358094
- Publication date Dec 13, 2018
- Micron Technology, Inc.
- Mario Allegra
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL ARCHITECTURE FOR MULTILEVEL CELL PROGRAMMING
- Publication number 20170236584
- Publication date Aug 17, 2017
- Micron Technology, Inc.
- Mario Allegra
- G11 - INFORMATION STORAGE

Mario Allegra

Person

Patents Grantslast 30 patents

Adaptive write operations for a memory device

Implementations to store fuse data in memory devices

Techniques to access a self-selecting memory device

Chalcogenide-based memory architecture

Adaptive write operations for a memory device

Techniques to access a self-selecting memory device

Dedicated read voltages for data structures

Implementations to store fuse data in memory devices

Chalcogenide-based memory architecture

Memory cell architecture for multilevel cell programming

Techniques to access a self-selecting memory device

Dedicated read voltages for data structures

Techniques to access a self-selecting memory device

Memory cell architecture for multilevel cell programming

Memory cell architecture for multilevel cell programming

Memory cell architecture for multilevel cell programming

Patents Applicationslast 30 patents

ADAPTIVE WRITE OPERATIONS FOR A MEMORY DEVICE

PHASE-CHANGE MEMORY CELL WITH ASYMMETRIC STRUCTURE, A MEMORY DEVICE...

TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE

ADAPTIVE WRITE OPERATIONS FOR A MEMORY DEVICE

IMPLEMENTATIONS TO STORE FUSE DATA IN MEMORY DEVICES

CHALCOGENIDE-BASED MEMORY ARCHITECTURE

ADAPTIVE WRITE OPERATIONS FOR A MEMORY DEVICE

IMPLEMENTATIONS TO STORE FUSE DATA IN MEMORY DEVICES

TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE

DEDICATED READ VOLTAGES FOR DATA STRUCTURES

CHALCOGENIDE-BASED MEMORY ARCHITECTURE

DEDICATED READ VOLTAGES FOR DATA STRUCTURES

TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE

MEMORY CELL ARCHITECTURE FOR MULTILEVEL CELL PROGRAMMING

TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE

MEMORY CELL ARCHITECTURE FOR MULTILEVEL CELL PROGRAMMING

MEMORY CELL ARCHITECTURE FOR MULTILEVEL CELL PROGRAMMING