Mark A. Armstrong

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Planar buried channel structure integrated with non-planar structures
- Patent number 12,205,947
- Issue date Jan 21, 2025
- Intel Corporation
- Guannan Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated nanowire and nanoribbon patterning in transistor manufac...
- Patent number 12,014,959
- Issue date Jun 18, 2024
- Intel Corporation
- Leonard P Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET varactor quality factor improvement
- Patent number 11,961,836
- Issue date Apr 16, 2024
- Intel Corporation
- Hyung-Jin Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration methods to fabricate internal spacers for nanowire devices
- Patent number 11,869,939
- Issue date Jan 9, 2024
- Sony Group Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
FIN shaping using templates and integrated circuit structures resul...
- Patent number 11,749,733
- Issue date Sep 5, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried channel structure integrated with non-planar structures
- Patent number 11,728,335
- Issue date Aug 15, 2023
- Intel Corporation
- Guannan Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned nanowire
- Patent number 11,715,787
- Issue date Aug 1, 2023
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field-effect transistors with asymmetric gate stacks
- Patent number 11,515,424
- Issue date Nov 29, 2022
- Intel Corporation
- Said Rami
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration methods to fabricate internal spacers for nanowire devices
- Patent number 11,302,777
- Issue date Apr 12, 2022
- Sony Group Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Fin shaping using templates and integrated circuit structures resul...
- Patent number 11,302,790
- Issue date Apr 12, 2022
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned nanowire
- Patent number 11,205,715
- Issue date Dec 21, 2021
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated nanowire and nanoribbon patterning in transistor manufac...
- Patent number 11,164,790
- Issue date Nov 2, 2021
- Intel Corporation
- Leonard P Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual mode snap back circuit device
- Patent number 11,152,352
- Issue date Oct 19, 2021
- Intel Corporation
- Akm Ahsan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field-effect transistors with dual thickness gate dielectrics
- Patent number 11,145,732
- Issue date Oct 12, 2021
- Intel Corporation
- Ayan Kar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration methods to fabricate internal spacers for nanowire devices
- Patent number 10,804,357
- Issue date Oct 13, 2020
- Sony Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Reduced punchthrough breakdown in gallium-nitride transistors
- Patent number 10,615,280
- Issue date Apr 7, 2020
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration methods to fabricate internal spacers for nanowire devices
- Patent number 10,580,860
- Issue date Mar 3, 2020
- Intel Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Integration methods to fabricate internal spacers for nanowire devices
- Patent number 10,283,589
- Issue date May 7, 2019
- Intel Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Integration methods to fabricate internal spacers for nanowire devices
- Patent number 10,121,856
- Issue date Nov 6, 2018
- Intel Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Systems and methods for determining and sending a preferred of two...
- Patent number 9,911,128
- Issue date Mar 6, 2018
- The Rocket Science Group LLC
- Ben Chestnut
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integration methods to fabricate internal spacers for nanowire devices
- Patent number 9,859,368
- Issue date Jan 2, 2018
- Intel Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Leakage reduction structures for nanowire transistors
- Patent number 9,825,130
- Issue date Nov 21, 2017
- Intel Corporation
- Seiyon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration methods to fabricate internal spacers for nanowire devices
- Patent number 9,484,447
- Issue date Nov 1, 2016
- Intel Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Mobile kiosk system
- Patent number 8,280,775
- Issue date Oct 2, 2012
- Mark Armstrong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CMOS fabrication process utilizing special transistor orientation
- Patent number 7,888,710
- Issue date Feb 15, 2011
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Restaurant kiosk
- Patent number D625304
- Issue date Oct 12, 2010
- Mark Armstrong
- D14 - Recording, communication, or information retrieval equipment
Information Patent Grant
Restaurant system
- Patent number 7,584,119
- Issue date Sep 1, 2009
- Mark Armstrong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhancing strained device performance by use of multi narrow sectio...
- Patent number 7,482,670
- Issue date Jan 27, 2009
- Intel Corporation
- Giuseppe Curello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of manufacturing a stressed MOS transistor structure
- Patent number 7,338,847
- Issue date Mar 4, 2008
- Intel Corporation
- M. Reaz Shaheed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS fabrication process utilizing special transistor orientation
- Patent number 7,312,485
- Issue date Dec 25, 2007
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20240153995
- Publication date May 9, 2024
- SONY GROUP CORPORATION
- Seiyon KIM
- B82 - NANO-TECHNOLOGY
Information Patent Application
MULTI-LAYERED SOURCE AND DRAIN CONTACTS FOR A THIN FILM TRANSISTOR...
- Publication number 20230369426
- Publication date Nov 16, 2023
- Intel Corporation
- Abhishek Anil Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LATERALLY RECESSED GATE ELECTRODE IN THIN FILM TRANSISTORS
- Publication number 20230369506
- Publication date Nov 16, 2023
- Intel Corporation
- Abhishek Anil Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-TIER MEMORY STRUCTURE WITH GRADED CHARACTERISTICS
- Publication number 20230371233
- Publication date Nov 16, 2023
- Intel Corporation
- Abhishek Anil Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYERED OR GRADED GATE DIELECTRIC IN THIN FILM TRANSISTOR (TF...
- Publication number 20230369444
- Publication date Nov 16, 2023
- Intel Corporation
- Abhishek Anil Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BURIED CHANNEL STRUCTURE INTEGRATED WITH NON-PLANAR STRUCTURES
- Publication number 20230317720
- Publication date Oct 5, 2023
- Intel Corporation
- Guannan LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DECOUPLING CAPACITORS AND METHODS OF FABRICATION
- Publication number 20220415896
- Publication date Dec 29, 2022
- Intel Corporation
- Juan G. Alzate-Vinasco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20220262901
- Publication date Aug 18, 2022
- SONY GROUP CORPORATION
- Seiyon KIM
- B82 - NANO-TECHNOLOGY
Information Patent Application
FIN SHAPING USING TEMPLATES AND INTEGRATED CIRCUIT STRUCTURES RESUL...
- Publication number 20220199792
- Publication date Jun 23, 2022
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED NANOWIRE & NANORIBBON PATTERNING IN TRANSISTOR MANUFACTURE
- Publication number 20220051946
- Publication date Feb 17, 2022
- Intel Corporation
- Leonard P/ Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED NANOWIRE
- Publication number 20220052178
- Publication date Feb 17, 2022
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD-EFFECT TRANSISTORS WITH DUAL THICKNESS GATE DIELECTRICS
- Publication number 20210167180
- Publication date Jun 3, 2021
- Intel Corporation
- Ayan Kar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20210050418
- Publication date Feb 18, 2021
- Sony Corporation
- Seiyon KIM
- B82 - NANO-TECHNOLOGY
Information Patent Application
FIN SHAPING USING TEMPLATES AND INTEGRATED CIRCUIT STRUCTURES RESUL...
- Publication number 20200388689
- Publication date Dec 10, 2020
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL MODE SNAP BACK CIRCUIT DEVICE
- Publication number 20200312838
- Publication date Oct 1, 2020
- Intel Corporation
- Akm Ahsan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD-EFFECT TRANSISTORS WITH ASYMMETRIC GATE STACKS
- Publication number 20200259018
- Publication date Aug 13, 2020
- Intel Corporation
- Said Rami
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BURIED CHANNEL STRUCTURE INTEGRATED WITH NON-PLANAR STRUCTURES
- Publication number 20200243517
- Publication date Jul 30, 2020
- Intel Corporation
- Guannan LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED NANOWIRE & NANORIBBON PATTERNING IN TRANSISTOR MANUFACTURE
- Publication number 20200176321
- Publication date Jun 4, 2020
- Intel Corporation
- Leonard P/ Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED NANOWIRE
- Publication number 20200152767
- Publication date May 14, 2020
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20200152738
- Publication date May 14, 2020
- Intel Corporation
- Seiyon KIM
- B82 - NANO-TECHNOLOGY
Information Patent Application
FINFET VARACTOR QUALITY FACTOR IMPROVEMENT
- Publication number 20200105747
- Publication date Apr 2, 2020
- Intel Corporation
- Hyung-Jin LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20190214461
- Publication date Jul 11, 2019
- Intel Corporation
- Seiyon KIM
- B82 - NANO-TECHNOLOGY
Information Patent Application
REDUCED PUNCHTHROUGH BREAKDOWN IN GALLIUM-NITRIDE TRANSISTORS
- Publication number 20190088773
- Publication date Mar 21, 2019
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20190051725
- Publication date Feb 14, 2019
- Intel Corporation
- Seiyon KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20180122901
- Publication date May 3, 2018
- Intel Corporation
- Seiyon KIM
- B82 - NANO-TECHNOLOGY
Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20170047400
- Publication date Feb 16, 2017
- Intel Corporation
- Seiyon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEAKAGE REDUCTION STRUCTURES FOR NANOWIRE TRANSISTORS
- Publication number 20140264253
- Publication date Sep 18, 2014
- Seiyon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Online Booking System
- Publication number 20140095217
- Publication date Apr 3, 2014
- Mark Armstrong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
- Publication number 20140001441
- Publication date Jan 2, 2014
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Application
Systems and Methods for Sending an Electronic Mail Communication at...
- Publication number 20110252107
- Publication date Oct 13, 2011
- THE ROCKET SCIENCE GROUP, LLC
- Ben Chestnut
- G06 - COMPUTING CALCULATING COUNTING

Mark A. Armstrong

Person

Patents Grantslast 30 patents

Planar buried channel structure integrated with non-planar structures

Integrated nanowire and nanoribbon patterning in transistor manufac...

FinFET varactor quality factor improvement

Integration methods to fabricate internal spacers for nanowire devices

FIN shaping using templates and integrated circuit structures resul...

Buried channel structure integrated with non-planar structures

Self-aligned nanowire

Field-effect transistors with asymmetric gate stacks

Integration methods to fabricate internal spacers for nanowire devices

Fin shaping using templates and integrated circuit structures resul...

Self-aligned nanowire

Integrated nanowire and nanoribbon patterning in transistor manufac...

Dual mode snap back circuit device

Field-effect transistors with dual thickness gate dielectrics

Integration methods to fabricate internal spacers for nanowire devices

Reduced punchthrough breakdown in gallium-nitride transistors

Integration methods to fabricate internal spacers for nanowire devices

Integration methods to fabricate internal spacers for nanowire devices

Integration methods to fabricate internal spacers for nanowire devices

Systems and methods for determining and sending a preferred of two...

Integration methods to fabricate internal spacers for nanowire devices

Leakage reduction structures for nanowire transistors

Integration methods to fabricate internal spacers for nanowire devices

Mobile kiosk system

CMOS fabrication process utilizing special transistor orientation

Restaurant kiosk

Restaurant system

Enhancing strained device performance by use of multi narrow sectio...

Methods of manufacturing a stressed MOS transistor structure

CMOS fabrication process utilizing special transistor orientation

Patents Applicationslast 30 patents

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

MULTI-LAYERED SOURCE AND DRAIN CONTACTS FOR A THIN FILM TRANSISTOR...

LATERALLY RECESSED GATE ELECTRODE IN THIN FILM TRANSISTORS

MULTI-TIER MEMORY STRUCTURE WITH GRADED CHARACTERISTICS

MULTI-LAYERED OR GRADED GATE DIELECTRIC IN THIN FILM TRANSISTOR (TF...

BURIED CHANNEL STRUCTURE INTEGRATED WITH NON-PLANAR STRUCTURES

DECOUPLING CAPACITORS AND METHODS OF FABRICATION

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

FIN SHAPING USING TEMPLATES AND INTEGRATED CIRCUIT STRUCTURES RESUL...

INTEGRATED NANOWIRE & NANORIBBON PATTERNING IN TRANSISTOR MANUFACTURE

SELF-ALIGNED NANOWIRE

FIELD-EFFECT TRANSISTORS WITH DUAL THICKNESS GATE DIELECTRICS

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

FIN SHAPING USING TEMPLATES AND INTEGRATED CIRCUIT STRUCTURES RESUL...

DUAL MODE SNAP BACK CIRCUIT DEVICE

FIELD-EFFECT TRANSISTORS WITH ASYMMETRIC GATE STACKS

BURIED CHANNEL STRUCTURE INTEGRATED WITH NON-PLANAR STRUCTURES

INTEGRATED NANOWIRE & NANORIBBON PATTERNING IN TRANSISTOR MANUFACTURE

SELF-ALIGNED NANOWIRE

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

FINFET VARACTOR QUALITY FACTOR IMPROVEMENT

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

REDUCED PUNCHTHROUGH BREAKDOWN IN GALLIUM-NITRIDE TRANSISTORS

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

LEAKAGE REDUCTION STRUCTURES FOR NANOWIRE TRANSISTORS

Online Booking System

INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES

Systems and Methods for Sending an Electronic Mail Communication at...