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Mark A. Warriner
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Ottawa, CA
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Patents Grants
last 30 patents
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Patent Grant
Method of speeding up output alignment in a digital phase locked loop
Patent number
10,069,503
Issue date
Sep 4, 2018
Microsemi Semiconductor ULC
Changhui Cathy Zhang
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Digital phase locked loop arrangement with master clock redundancy
Patent number
9,595,972
Issue date
Mar 14, 2017
Microsemi Semiconductor ULC
Slobodan Milijevic
H03 - BASIC ELECTRONIC CIRCUITRY
Patents Applications
last 30 patents
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Patent Application
METHOD OF SPEEDING UP OUTPUT ALIGNMENT IN A DIGITAL PHASE LOCKED LOOP
Publication number
20170346494
Publication date
Nov 30, 2017
MICROSEMI SEMICONDUCTOR ULC
Changhui Cathy Zhang
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Application
Digital Phase Locked Loop Arrangement with Master Clock Redundancy
Publication number
20160301416
Publication date
Oct 13, 2016
MICROSEMI SEMICONDUCTOR ULC
Slobodan Milijevic
H03 - BASIC ELECTRONIC CIRCUITRY